Electronic systems installed in their operation environments often require regular testing. The nanometer transistor size in new IC design technologies makes the electronic systems more vulnerable to defects. Due to certain reasons like wear out or over heating and difficulty to access systems in remote areas, in-field testing is vital. For in-field testing, embedded test controllers are more effective in terms of maintenance cost than external testers. For in-field testing, fault coverage, high memory requirements, test application time, flexibility and diagnosis are the main challenges. In this thesis, an Embedded Test Controller (ETC) is designed and implemented which provides flexible in-field testing and diagnostic capability with high fault coverage. The ETC has relatively low memory requirements for storing deterministic test data as compared to storing complete test vectors. The test patterns used by the ETC are stored separately for each component of the device under test, in system memory. The test patterns for each component are concatenated during test application according to a flexible test command. To address test application time (which corresponds to down time of the system), two different versions of the ETC are designed and implemented. These versions provide a trade off between test application time and hardware overhead. Hence, a system integrator can select which version to use depending on the cost factors at hand. The ETC can make use of an embedded CPU in the Device Under Test (DUT), for performing test on the DUT. For DUTs where no embedded CPU is available, there is the additional cost of a test specific CPU for the ETC. To access the DUT during the test application, the IEEE 1149.1 (JTAG) interface is used. The ETC generates test result that provides information of failing ICs and patterns. The designed and implemented versions of the ETC are validated through experimentations. An FPGA platform is used for experimental validation of the ETC versions. A set of tools are developed for automating the experimental setup. Performance and hardware cost of the ETC versions are evaluated using the ITC'02 benchmarks.

Abstract This thesis studies the methods to test mixed-signal devices and circuits on board and system level with embedded test instrumentation. The study is divided in three continuous sections, development of embedded test methods for discrete components, integration of test instruments on board level and development of test and health monitoring strategy for large scale system. The developed embedded test methods for mixed signal circuitry on board level are based on the standard for mixed signal test bus IEEE 1149.4. The standardized embedded test infrastructure is utilized for testing discrete components with emphasis on testing active components as diodes and transistors. The developed embedded tests are evaluated with PCOLA/SOQ method for manufacturing testing and also the usability of the tests is discussed. A solution for embedded mixed-signal test controller is presented with discussion of test communication and the possibilities of implementing embedded test control. The target in the development of the test control is to enable launch mixed signal tests on device remotely. The test controller is IEEE 1149.4 compatible and can generate and measure analog test signals while controlling boundary-scan enabled devices. The final section of the thesis focuses on an embedded test solution for aerospace bus system (MIL-STD-1553). Current solutions are based on testing the bus system during maintenance on ground. The developed test and monitoring method allows on-line monitoring of the bus to detect and locate possible defects which only occur during use of the aeroplane. / Tiivistelmä Väitöstyössä tutkittiin sekasignaalilaitteiden ja -piirien testausmenetelmiä levy- ja järjestelmätasolla hyödyntäen sulautettuja testilaitteita. Työ jakaantuu kolmeen osaan; sulautettujen testausmenetelmien kehitys diskreeteille komponenteille, testi-instrumenttien integrointi piirilevytasolle sekä testaus- ja kunnonmonitorointimenetelmän kehitys laajemmalle järjestelmälle. Sulautettujen testimenetelmien kehitys sekasignaalipiireille piirilevytasolla perustuu sekasignaalitestiväylän standardiin IEEE 1149.4. Standardoitua sulautettua testi-infrastruktuuria käytettiin diskreettien komponenttien testaukseen painottuen aktiivikomponentteihin, kuten diodeihin ja transistoreihin. Kehitetyt sulautetut testit on arvioitu PCOLA/SOQ menetelmällä, jota hyödynnetään tuotantotestauksen testikattavuuden arvioinnissa. Lisäksi testimenetelmien käytettävyyttä arvioitiin. Sulautettu sekasignaalilaitteiden testikontrollerin tavoite on käynnistää ja suorittaa sekasignaalitestejä laitteessa etäältä. Kehitetty testikontrolleri on IEEE 1149.4 yhteensopiva ja voi generoida ja mitata analogista testisignaalia sekä samanaikaisesti ohjata testiväylää. Lisäksi etätestauksen mahdollistavasta testikommunikaatiomenetelmiä arvioitiin kuten myös erilaisia toteutustasoja sulautetuille testimenetelmille. Laajemman järjestelmän kehityksessä tutkittiin sulautettua testausratkaisua lentokoneen väyläjärjestelmälle, joka perustuu standardiin MIL-STD-1553B. Nykyiset menetelmät perustuvat väyläjärjestelmän testaukseen huollon yhteydessä, mutta osa virheistä ilmenee vain käytön aikana. Kehitetty testaus- ja monitorointimenetelmä mahdollistaa käytönaikaisen jatkuvan virheiden monitoroinnin sekä niiden paikantamisen lennon aikana.

<p>Embedded and automated tests reduce maintenance costs for embedded systems installed in remote locations. Testing multiple components of an embedded system, connected on a scan chain, using deterministic test patterns stored in a system provide high fault coverage but require large system memory. This thesis presents an approach to reduce test data memory requirements by the use of a test controller program, utilizing the observation of that there are multiple components of the same type in a system. The program use deterministic test patterns specific to every component type, which is stored in system memory, to create fully defined test patterns when needed. By storing deterministic test patterns specific to every component type, the program can use the test patterns for multiple tests and several times within the same test. The program also has the ability to test parts of a system without affecting the normal functional operation of the rest of the components in the system and without an increase of test data memory requirements. Two experiments were conducted to determine how much test data memory requirements are reduced using the approach presented in this thesis. The results for the experiments show up to 26.4% reduction of test data memory requirements for ITC´02 SOC test benchmarks and in average 60% reduction of test data memory requirements for designs generated to gain statistical data.</p>

Embedded and automated tests reduce maintenance costs for embedded systems installed in remote locations. Testing multiple components of an embedded system, connected on a scan chain, using deterministic test patterns stored in a system provide high fault coverage but require large system memory. This thesis presents an approach to reduce test data memory requirements by the use of a test controller program, utilizing the observation of that there are multiple components of the same type in a system. The program use deterministic test patterns specific to every component type, which is stored in system memory, to create fully defined test patterns when needed. By storing deterministic test patterns specific to every component type, the program can use the test patterns for multiple tests and several times within the same test. The program also has the ability to test parts of a system without affecting the normal functional operation of the rest of the components in the system and without an increase of test data memory requirements. Two experiments were conducted to determine how much test data memory requirements are reduced using the approach presented in this thesis. The results for the experiments show up to 26.4% reduction of test data memory requirements for ITC´02 SOC test benchmarks and in average 60% reduction of test data memory requirements for designs generated to gain statistical data.

Η διατριβή ασχολείται με το αντικείμενο του ελέγχου ορθής λειτουργίας κυκλωμάτων κατά τον οποίο λαμβάνεται υπόψη και η συμπεριφορά ως προς την κατανάλωση ισχύος. Οι τεχνικές που προτείνονται αφορούν α) τη συμπίεση ενός συνόλου δοκιμής σε περιβάλλον ενσωματωμένου ελέγχου με χρήση εξωτερικών ελεγκτών, β) την εμφώλευση διανυσμάτων δοκιμής σε περιβάλλον ενσωματωμένου ελέγχου και γ) τη μείωση της κατανάλωση ισχύς και ενέργειας σε περιβάλλον εξωτερικού ελέγχου. Η συμπίεση των δεδομένων βασίζεται στην παρατήρηση ότι ένα διάνυσμα δοκιμής μπορεί να παραχθεί από το προηγούμενό του με την αντικατάσταση κάποιων τμημάτων του. Μεγαλύτερη συμπίεση επιτυγχάνεται όταν γίνει αναδιαταξή διανυσμάτων και αναδιάταξη των φλιπ-φλοπ της αλυσίδας ανίχνευσης. Αν η αναδιάταξη των φλιπ-φλοπ γίνει με βάση τη συχνότητα αλλαγών κατάστασης γειτονικών φλιπ-φλοπ τότε επιτυγχάνεται και μείωση της κατανάλωσης ισχύος. Όσον αφορά τις τεχνικές ενσωματωμένου αυτοελέγχου, μελετήθηκε το πρόβλημα της εμφώλευσης διανυσμάτων δοκιμής. Προτάθηκαν αποδοτικά κυκλώματα παραγωγής διανυσμάτων δοκιμής βασισμένα σε ολισθητές γραμμικής ανάδρασης και δέντρα πυλών XOR και σε ολισθητές συνδυασμένους με δέντρα πυλών OR. Όταν τα κυκλώματα υπό έλεγχο είναι κανονικής μορφής όπως είναι οι αθροιστές του αριθμητικού συστήματος υπολοίπων, προτείνονται κυκλώματα που εκμεταλεύονται την κανονική μορφή του συνόλου δοκιμής. Τέλος, σε περιβάλλον εξωτερικού ελέγχου, προτείνονται μέθοδοι αναδιάταξης διανυσμάτων δοκιμής με επανάληψη διανυσμάτων που μειώνουν την κατανάλωση. Οι μέθοδοι αυτές βασίζονται στην επιλογή των κατάλληλων ελάχιστων γεννητικών δέντρων και στη μετατροπή των κατάλληλων επαναλαμβανόμενων διανυσμάτων επιτυγχάνοντας σημαντική μείωση στην κατανάλωση ενέργειας, στη μέση και στη μέγιστη κατανάλωση ισχύος. / The dissertation is focused on VLSI testing while power dissipation is also taken into account. The techniques proposed are: a) test data compression in an embedded test environment, b) test set embedding in a built-in self test environment and c) reduction in test power dissipation in an external testing environment. Test data compression is based on the observation that a test vector can be produced from the previous one by replacing some parts of the previous vector with new parts of the current vector. The compression is even higher when the test vectors are ordered and scan cell reordering is also performed. If the scan cell reordering is based on a transition frequency approach then reduction in power dissipation is also achieved. In the case of built-in self test the problem of test set embedding was studied and efficient circuits based on linear feedback shift registers combined with XOR trees or shift registers combined with OR trees were proposed. If the circuits have a regular structure, such as the structure of residue number system adders, then a circuit taking advantage of the regular form of the test set can be derived. Finally, when external testing is considered, we proposed test vector ordering with vector repetition methods, which reduce power consumption. The methods are based on the selection of the appropriate minimum spanning trees and through the modification of the repeated vectors they achieve considerable savings in energy, average and peak power dissipation.