Primitivas criptografias assimétricas são essenciais para conseguir comunicação segura numa rede ou meio público. Essas primitivas podem ser instaladas como bibliotecas de software ou como coprocessadores de hardware. Coprocessadores de hardware são muito utilizados em cenários como Systems on Chip (SoC), dispositivos embarcados ou servidores de aplicações específicas. Coprocessadores existentes baseados em RSA ou curvas ellipticas (ECC) fazem um processamento intenso por causa da aritmética modular de grande precisão, portanto não estão disponíveis em plataformas com quantidade de energia mais restrita. Para prover primitivas assimétricas para esses dispositivos, será avaliado um esquema de cifração assimétrica que utiliza artimética de pequena precisão, chamado McEliece. McEliece foi proposto com códigos de Goppa binários durante o mesmo ano que o RSA, porém com chaves públicas 50 vezes maiores. Por causa de chaves tão grandes ele não ganhou muita atenção como RSA e ECC. Com a adoção de códigos Quase-Diádicos de Goppa binários é possível obter níveis de segurança práticos com chaves relativamente pequenas. Para avaliar uma implementação em hardware para esse esquema, foi proposto uma arquitetura escalável que pode ser configurada de acordo com os requisitos do projeto. Essa arquitetura pode ser utilizada em todos os níveis de segurança, de 80 até 256 bits de segurança, da menor unidade até as maiores. Nossa arquitetura foi implementada na família de FPGAs Spartan 3 para códigos de Goppa binários, onde foi possível decifrar em 5854 ciclos com 4671 Slices, enquanto que na literatura os melhores resultados obtidos são de 10940 ciclos para 7331 Slices. / Asymmetric cryptographic primitives are essential to enable secure communications on public networks or public mediums. These cryptographic primitives can be deployed as software libraries or hardware coprocessors. Hardware coprocessors are mostly employed in Systems on Chip (SoC) scenarios, embedded devices, or application-specific servers. Available solutions based on RSA or Elliptic Curve Cryptography (ECC) are highly processing intensive because of the underlying extended precision modular arithmetic, and hence they are not available on the most energy constrained platforms. To provide asymmetric primitives in those restricted devices, we evaluate another asymmetric encryption scheme implementable with lightweight arithmetic, called McEliece. McEliece was proposed with binary Goppa codes during same year of RSA with public keys 50 times larger. Because of such large keys it has not gained as much attention as RSA or ECC. With the adoption of binary Quasi- Dyadic Goppa (QD-Goppa) codes it is possible to attain practical security levels with reasonably small keys. To evaluate a hardware implementation of this scheme, we investigate a scalable architecture that can be reconfigured according to project requirements. This architecture is suitable for all usual security levels, from 80 to 256-bit security, from the smallest unit to bigger ones. With our architecture implemented on a Spartan 3 FPGA for binary Goppa codes it is possible to decrypt in 5854 cycles with 4671 Slices, whilst in literature best results were in 10940 cycles with 7331 Slices.

Zhao Fei. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 87-89). / Abstracts in English and Chinese. / Chapter 1. --- Introduction --- p.1 / Chapter 1.1 --- Multirate Scheme --- p.2 / Chapter 1.1.1 --- VSF Scheme --- p.3 / Chapter 1.1.2 --- Multicode Scheme --- p.5 / Chapter 1.2 --- Multicode CDMA System --- p.7 / Chapter 1.2.1 --- System Model --- p.7 / Chapter 1.2.2 --- Envelope Variation of Multicode Signal --- p.9 / Chapter 1.2.3 --- Drawback of Multicode Scheme --- p.11 / Chapter 1.3 --- Organization of the Thesis --- p.13 / Chapter 2. --- Related Work on Minimization of PAP of Multicode CDMA --- p.15 / Chapter 2.1 --- Constant Amplitude Coding --- p.16 / Chapter 2.2 --- Multidimensional Multicode Scheme --- p.22 / Chapter 2.3 --- Precoding for Multicode Scheme --- p.25 / Chapter 2.4 --- Summary --- p.26 / Chapter 3. --- Multicode CDMA System with Constant Amplitude Transmission --- p.27 / Chapter 3.1 --- System Model --- p.28 / Chapter 3.2 --- Selection of Hadamard Code Sequences --- p.31 / Chapter 3.3 --- The Optimal Receiver for the Multicode System --- p.37 / Chapter 3.3.1 --- The Maximum-Likelihood Sequence Detector --- p.38 / Chapter 3.3.2 --- Maximum A Posteriori Probability Detector --- p.41 / Chapter 4. --- Multicode CDMA System Combined with Error-Correcting Codes --- p.45 / Chapter 4.1 --- Hamming Codes --- p.46 / Chapter 4.2 --- Gallager's Codes --- p.48 / Chapter 4.2.1 --- Encoding of Gallager's Codes --- p.48 / Chapter 4.2.2 --- Multicode Scheme combined with Gallager's Code --- p.52 / Chapter 4.2.3 --- Iterative Decoding of the Multicode Scheme --- p.55 / Chapter 4.3 --- Zigzag Codes --- p.59 / Chapter 4.4 --- Simulation Results and Discussion --- p.62 / Chapter 5. --- Multicode CDMA System with Bounded PAP Transmission --- p.68 / Chapter 5.1 --- Quantized Multicode Scheme --- p.69 / Chapter 5.1.1 --- System Model --- p.69 / Chapter 5.1.2 --- Interference of Code Channels --- p.71 / Chapter 5.2 --- Parallel Multicode Scheme --- p.74 / Chapter 5.2.1 --- System Model --- p.74 / Chapter 5.2.2 --- Selection of Hadamard Code Sequences --- p.75 / Chapter 6. --- Conclusions and Future Work --- p.82 / Chapter 6.1 --- Conclusions --- p.82 / Chapter 6.2 --- Future Work --- p.84 / Bibliography --- p.87

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1981. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / by Richard Michael Heller. / B.S.

Primitivas criptografias assimétricas são essenciais para conseguir comunicação segura numa rede ou meio público. Essas primitivas podem ser instaladas como bibliotecas de software ou como coprocessadores de hardware. Coprocessadores de hardware são muito utilizados em cenários como Systems on Chip (SoC), dispositivos embarcados ou servidores de aplicações específicas. Coprocessadores existentes baseados em RSA ou curvas ellipticas (ECC) fazem um processamento intenso por causa da aritmética modular de grande precisão, portanto não estão disponíveis em plataformas com quantidade de energia mais restrita. Para prover primitivas assimétricas para esses dispositivos, será avaliado um esquema de cifração assimétrica que utiliza artimética de pequena precisão, chamado McEliece. McEliece foi proposto com códigos de Goppa binários durante o mesmo ano que o RSA, porém com chaves públicas 50 vezes maiores. Por causa de chaves tão grandes ele não ganhou muita atenção como RSA e ECC. Com a adoção de códigos Quase-Diádicos de Goppa binários é possível obter níveis de segurança práticos com chaves relativamente pequenas. Para avaliar uma implementação em hardware para esse esquema, foi proposto uma arquitetura escalável que pode ser configurada de acordo com os requisitos do projeto. Essa arquitetura pode ser utilizada em todos os níveis de segurança, de 80 até 256 bits de segurança, da menor unidade até as maiores. Nossa arquitetura foi implementada na família de FPGAs Spartan 3 para códigos de Goppa binários, onde foi possível decifrar em 5854 ciclos com 4671 Slices, enquanto que na literatura os melhores resultados obtidos são de 10940 ciclos para 7331 Slices. / Asymmetric cryptographic primitives are essential to enable secure communications on public networks or public mediums. These cryptographic primitives can be deployed as software libraries or hardware coprocessors. Hardware coprocessors are mostly employed in Systems on Chip (SoC) scenarios, embedded devices, or application-specific servers. Available solutions based on RSA or Elliptic Curve Cryptography (ECC) are highly processing intensive because of the underlying extended precision modular arithmetic, and hence they are not available on the most energy constrained platforms. To provide asymmetric primitives in those restricted devices, we evaluate another asymmetric encryption scheme implementable with lightweight arithmetic, called McEliece. McEliece was proposed with binary Goppa codes during same year of RSA with public keys 50 times larger. Because of such large keys it has not gained as much attention as RSA or ECC. With the adoption of binary Quasi- Dyadic Goppa (QD-Goppa) codes it is possible to attain practical security levels with reasonably small keys. To evaluate a hardware implementation of this scheme, we investigate a scalable architecture that can be reconfigured according to project requirements. This architecture is suitable for all usual security levels, from 80 to 256-bit security, from the smallest unit to bigger ones. With our architecture implemented on a Spartan 3 FPGA for binary Goppa codes it is possible to decrypt in 5854 cycles with 4671 Slices, whilst in literature best results were in 10940 cycles with 7331 Slices.

Abstract not available

Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. This thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. Cycles of length four are avoided by observing the row-column constraint. Row-column connections observing this condition are searched sequentially or randomly. Although the girth conditions are not sufficient beyond six, larger girths codes were easily obtained especially at low rates. The advantage of this algorithm compared to other methods is its flexibility. It could be used to construct codes for a given rate and length with girths of at least six for any sub-matrix configuration or rearrangement. The code size is also easily varied by increasing or decreasing sub-matrix size. Codes obtained using a sequential search criteria show poor performance at low girths (6 and 8) while random searches result in good performing codes. Quasi-cyclic codes could be implemented in a variety of decoder architectures. One of the many options is the choice of processing nodes interconnect. We show how quasi-cyclic codes processing could be scheduled through a multistage network. Although these net-works have more delay than other modes of communication, they offer more flexibility at a reasonable cost. Banyan and Benes networks are suggested as the most suitable networks. Decoding delay is also one of several issues considered in decoder design and implementation. In this thesis, we overlap check and variable node computations to reduce decoding time. Three techniques are discussed, two of which are introduced in this thesis. The techniques are code matrix permutation, matrix space restriction and sub-matrix row-column scheduling. Matrix permutation rearranges the parity-check matrix such that rows and columns that do not have connections in common are separated. This techniques can be applied to any matrix. Its effectiveness largely depends on the structure of the code. We show that its success also depends on the size of row and column weights. Matrix space restriction is another technique that can be applied to any code and has fixed reduction in time or amount of overlap. Its success depends on the amount of restriction and may be traded with performance loss. The third technique already suggested in literature relies on the internal cyclic structure of sub-matrices to achieve overlapping. The technique is limited to LDPC code matrices in which the number of sub-matrices is equal to row and column weights. We show that it can be applied to other codes with a lager number of sub-matrices than code weights. However, in this case maximum overlap is not guaranteed. We calculate the lower bound on the amount of overlapping. Overlapping could be applied to any sub-matrix configuration of quasi-cyclic codes by arbitrarily choosing the starting rows for processing. Overlapping decoding time depends on inter-iteration waiting times. We show that there are upper bounds on waiting times which depend on the code weights. Waiting times could be further reduced by restricting shifts in identity sub-matrices or using smaller sub-matrices. This overlapping technique can reduce the decoding time by up to 50% compared to conventional message and computation scheduling. Techniques of matrix permutation and space restriction results in decoder architectures that are flexible in LDPC code design in terms of code weights and size. This is due to the fact that with these techniques, rows and columns are processed in sequential order to achieve overlapping. However, in the existing technique, all sub-matrices have to be processed in parallel to achieve overlapping. Parallel processing of all code sub-matrices requires the architecture to have the number of processing units at least equal to the number sub-matrices. Processing units and memory space should therefore be distributed among the sub-matrices according to the sub-matrices arrangement. This leads to high complexity or inflexibility in the decoder architecture. We propose a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques. / Thesis(Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2007

This thesis shows how certain classes of binary constant weight codes can be represented geometrically using linear structures in Euclidean space. The geometric treatment is concerned mostly with codes with minimum distance 2(w - 1), that is, where any two codewords coincide in at most one entry; an algebraic generalization of parts of the theory also applies to some codes without this property. The presented theorems lead to a total of 18 improvements of the table of lower bounds on A(n,d,w) maintained by E. M. Rains and N. J. A. Sloane. Additional improvements have been made by finding new lexicographic codes.

Thesis (M.S.) -- Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

No description available.

Securing information during its storage and transmission is an important and widely addressed issue. Generally, cryptographic techniques are used for information security. Cryptography requires long keys which need to be kept secret in order to protect the information. The drawback of cryptography is that these keys are not strongly linked to the user identity. In order to strengthen the link between the user's identity and his cryptographic keys, biometrics is combined with cryptography. In this thesis, we present various methods to combine biometrics with cryptography. With this combination, we also address the privacy issue of biometric systems: revocability, template diversity, and privacy protection are added to the biometric verification systems. Finally, we also present a protocol for generating and sharing biometrics based crypto-biometric session keys. These systems are evaluated on publicly available iris and face databases