This thesis studies and compares existing Numerical Result checking algorithms for FFT computations under faults. In order to simulate faulty conditions, a fault injection tool is implemented. The fault injection tool is designed so as to be as non-intrusive to the application as possible. Faults are injected into memory in the form of bit flips in the data elements of the application. The performance of the three result checking algorithms under these conditions is studied and compared. Faults are injected at all the stages of the FFT computation by flipping each of the 64-bits in the double-precision representation. Experiments also include introducing random bit flips in the data array, emulating a more real-life like scenario. Finally the performance of these algorithms under a set of worst-case is also studied

Dolby AC-3, the audio signal compression standard adopted by the United States Advanced Television System Committee (ATSC), and wildly used in other applications DVD and digital TV. In order to improve the compression quality, the AC-3 defines two block lengths for IMDCT, one 512-pt.(long block) and the other 256-pt.(short block,). In the thesis, we realize the AC-3 audio decoder on the ARM-based platform. Our simulation results show that the IMDCT takes about 66% computation time of all decode process. Since the pure software decoding time cannot meet the real time requirement in many high speed applications, we design and implement the IMDCT hardware architecture considering of shore/long transform, the memory allocation for IMDCT, and use look-up tables to reduce the computation load. The HW/SW co-design on the ARM-based platform achieves the real-time requirements.

<p>This report deals with the modeling of a part of the communication system based on the IEEE 802.11a standard which represents the next generation of wireless LAN with greater scalability, better interference immunity and significantly higher speed, up to 54 Mbps. </p><p>802.11a uses Orthogonal Frequency Division Multiplexing (OFDM) where modulation is performed by an IFFT and the demodulation by an FFT. </p><p>After modeling the FFT in Matlab and C, the FFT implementation has been validated using a soft microprocessor core by Xilinx (Microblaze) and the results were compared.</p>

<p>This report has been compiled to document the thesis work carried out by Anton Andersson for Coresonic AB. The task was to develop an accelerator that could generate complex numbers suitable for fast fourier transforms (FFT) and tuning the phase of complex signals (NCO). Of many ways to achieve this, the CORDIC algorithm was chosen. It is very well suited since the basic implementation allows rotation of 2D-vectors using only shift and add operations. Error bounds and proof of convergence are derived carefully The accelerator was implemented in VHDL in such a way that all critical parameters were easy to change. Performance measures were extracted by simulating realistic test cases and then compare the output with reference data precomputed with high precision. Hardware costs were estimated by synthesizing a set of different configurations. Utilizing graphs of performance versus cost makes it possible to choose an optimal configuration. Maximum errors were extracted from simulations and seemed rather large for some configurations. The maximum error distribution was then plotted in histograms revealing that the typical error is often much smaller than the largest one. Even after trouble-shooting, the errors still seem to be somewhat larger than what other implementations of CORDIC achieve. However, precision was concluded to be sufficient for targeted applications.</p> / <p>Den här rapporten dokumenterar det examensarbete som utförts av AntonAndersson för Coresonic AB. Uppgiften bestod i att utveckla enaccelerator som kan generera komplexa tal som är lämpliga att använda försnabba fouriertransformer (FFT) och till fasvridning av komplexasignaler (NCO). Det finns en mängd sätt att göra detta men valet föllpå en algoritm kallad CORDIC. Den är mycket lämplig då den kan rotera2D-vektorer godtycklig vinkel med enkla operationer som bitskift ochaddition. Felgränser och konvergens härleds noggrannt. Acceleratorn implementerades i språket VHDL med målet att kritiskaparametrar enkelt skall kunna förändras. Därefter simuleradesmodellen i realistiska testfall och resulteten jämfördes medreferensdata som förberäknats med mycket hög precision. Dessutomsyntetiserades en mängd olika konfigurationer så att prestanda enkeltkan viktas mot kostnad.Ur de koefficienter som erhölls genom simuleringar beräknades detstörsta erhållna felet för en mängd olika konfigurationer. Felenverkade till en början onormalt stora vilket krävde vidareundersökning. Samtliga fel från en konfiguration ritades ihistogramform, vilket visade att det typiska felet oftast varbetydligt mindre än det största. Även efter felsökning verkar acceleratorngenerera tal med något större fel än andra implementationer avCORDIC. Precisionen anses dock vara tillräcklig för avsedda applikationer.</p>

<p>I detta projekt undersöker vi om man kan bygga en maskinaktivitetssensor med</p><p>hjälp av en enkretsdator som genom en accelerometer mäter en maskins</p><p>vibrationer. Sensorn skall generera en statussignal. Accelerometern ger en</p><p>mätbar signal baserad på maskinens vibrationer. Enkretsdatorn används för att</p><p>sampla, transformera och analysera signalen och generera statusinformation.</p><p>Med LabView kan vi spara, studera och analysera olika signaler och olika</p><p>transformer. Vi studerar maskinvibrationer i LabView och beslutar att 5 kHz</p><p>sampling räcker för att fånga intressanta vibrationer. Vi jämför transformers</p><p>egenskaper och beräkningskrav och väljer Fouriertransform som analysmetod.</p><p>Vi beräknar att en Atmel ARM SAM7S256 kan utföra uppgiften och</p><p>implementerar interruptbaserad signalsampling, frekvensanalys och en</p><p>beslutsrutin som resulterar i en utsignal med statusinformation.</p> / <p>In this project we examine the possibility to create a machine activity sensor by</p><p>a one-chip computer that measures a machines vibrations through an</p><p>accelerometer. The sensor shall generate a status signal. The accelerometer is</p><p>used to give a measurable signal of a machines vibrations. The one-chip</p><p>computer is used to sampel, transform and analyze this signal and generate a</p><p>status signal. With LabView we can save, study and analyze different signals</p><p>and their different transforms. By studying machine vibrations in LabView we</p><p>decide that sampling at 5 kHz is sufficient. By comparing different</p><p>transformations in regards to performance and calculation needs we choose</p><p>Fast Fourier Transform as analyzing tool. We calculate that a ARM</p><p>SAM7S256 can manage the task and implement an interrupt based sampling,</p><p>frequency analysis and decision making routine which results in a status signal.</p>

ITC/USA 2014 Conference Proceedings / The Fiftieth Annual International Telemetering Conference and Technical Exhibition / October 20-23, 2014 / Town and Country Resort & Convention Center, San Diego, CA / Data acquisition for flight test is typically handled by dedicated hardware which performs specific functions and targets specific interfaces and buses. Through the use of an FPGA state machine based design approach, performance and robustness can be guaranteed. Up to now sufficient flexibility has been provided by allowing the user to configure the hardware depending on the particular application. However by allowing custom algorithms to be run on the data acquisition hardware, far greater control and flexibility can be offered to the flight test engineer. As the volume of the acquired data increases, this extra control can be used to vastly reduce the amount of data to be recorded or telemetered. Also real-time analysis of test points can now be done where post processing would previously have been required. This paper examines examples of data acquisition, recording and processing and investigates where data reduction and time savings can be achieved by enabling the flight test engineer to run his own algorithms on the hardware.

The initial design of an OFDM transceiver is described and the simulations using MATLAB’s Simulink Software and other FGPA based tools are presented. All components of a modern OFDM system were implemented in Simulink to provide an understanding of the various components of an OFDM system, provide a proof of concept in the design, and measure the theoretical performance of the system. In an effort to build the transceiver, the FFT and randomizer components were implemented in verilog and were successfully simulated using ModelSim Altera Starter Edition 6.5b. A commercially available OFDM core, which did not include forward error correction, was simulated to measure the performance of an OFDM system within Altera Stratix III devices and determine the overall logic utilization for OFDM modulation and demodulation. The goals of this report are to describe in detail the general effort made by the author to build an OFDM transceiver and serve as a driver for its eventual FPGA implementation. / text

No description available.

There is a growing demand for high-speed arithmetic co-processors for use in applications with computationally intensive tasks. For instance, Fast Fourier Transform (FFT) co-processors are used in real-time multimedia services and financial applications use decimal co-processors to perform large amounts of decimal computations. Using redundant number systems to eliminate word-wide carry propagation within interim operations is a well-known technique to increase the speed of arithmetic hardware units. Redundant number systems are mostly useful in applications where many consecutive arithmetic operations are performed prior to the final result, making it advantageous for arithmetic co-processors. This thesis discusses the implementation of two popular arithmetic co-processors based on redundant number systems: namely, the binary FFT co-processor and the decimal arithmetic co-processor. FFT co-processors consist of several consecutive multipliers and adders over complex numbers. FFT architectures are implemented based on fixed-point and floating-point arithmetic. The main advantage of floating-point over fixed-point arithmetic is the wide dynamic range it introduces. Moreover, it avoids numerical issues such as scaling and overflow/underflow concerns at the expense of higher cost. Furthermore, floating-point implementation allows for an FFT co-processor to collaborate with general purpose processors. This offloads computationally intensive tasks from the primary processor. The first part of this thesis, which is devoted to FFT co-processors, proposes a new FFT architecture that uses a new Binary-Signed Digit (BSD) carry-limited adder, a new floating-point BSD multiplier and a new floating-point BSD three-operand adder. Finally, a new unit labeled as Fused-Dot-Product-Add (FDPA) is designed to compute AB+CD+E over floating-point BSD operands. The second part of the thesis discusses decimal arithmetic operations implemented in hardware using redundant number systems. These operations are popularly used in decimal floating-point co-processors. A new signed-digit decimal adder is proposed along with a sequential decimal multiplier that uses redundant number systems to increase the operational frequency of the multiplier. New redundant decimal division and square-root units are also proposed. The architectures proposed in this thesis were all implemented using Hardware-Description-Language (Verilog) and synthesized using Synopsys Design Compiler. The evaluation results prove the speed improvement of the new arithmetic units over previous pertinent works. Consequently, the FFT and decimal co-processors designed in this thesis work with at least 10% higher speed than that of previous works. These architectures are meant to fulfill the demand for the high-speed co-processors required in various applications such as multimedia services and financial computations.

A new, high resolution, high precision and accuracy gravimetric geoid of Australia has been produced using updated data, theory and computational methodologies. The fast Fourier transform technique is applied to the computation of the geoid and terrain effects. The long, medium and short wavelength components of the geoid are determined from the OSU91A global geopotential model, 2'x2' (residual gravity anomalies in a 3 degrees cap and 1'x1' digital terrain model (DTM), respectively.Satellite altimeter gravity data have been combined with marine gravity data to improve the coverage of the gravity data, and thus the quality of the geoid. The best gridding procedure for gravity data has been studied and applied to the gravity data gridding. It is found that the gravity field of Australia behaves quite differently. None of the free-air, Bouguer or topographic-isostatic gravity anomalies are consistently the smoothest. The Bouguer anomaly is often rougher than the free-air anomaly and thus should be not used for gravity field gridding. It is also revealed that in some regions the topography often contains longer wavelength features than the gravity anomalies.It is demonstrated that the inclusion of terrain effects is crucial for the determination of an accurate gravimetric geoid. Both the direct and indirect terrain effects need to be taken into account in the precise geoid determination of Australia. The existing AUSGEOID93 could be in error up to 0.7m in terms of the terrain effect only. In addition, a series of formulas have been developed to evaluate the precision of the terrain effects. These formulas allow the effectiveness of the terrain correction and precision requirement for a given DTM to be studied. It is recommended that the newly released 9"x9" DTM could be more effectively used if it is based on 15"x15" grid.It is estimated from comparisons with Global ++ / Positioning System (GPS) and Australian Height Datum Data that the absolute accuracy of the new geoid is better than 33cm and the relative precision of the new geoid is better than 10~20cm. This new geoid can support Australian GPS heighting to third-order specifications.