ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada / This design adopts the software radio and DBPSK（Differential Binary Phase Shift Keying）modulation-demodulation, which detects the telecommand receiving by the guided-missile system correctly. The DBPSK modulation module in Altera FPGA chip converts the binary telecommand into DBPSK signal, which will be frequency modulated after D/A conversion. In the receiver, the FM signal is demodulated and A/D converted before sending to the FPGA. The DBPSK demodulation module in FPGA finally gets the telecommand which will be tally with the telecommand from transmitter. At last, the whole DBPSK modulation-demodulation module is embedded into the remote control test system. The design is working properly and meeting the requirements of the test system.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / The advent of adaptive computers built from re-programmable logic devices presents a potential solution for meeting the data processing requirements of the new era of Earth monitoring satellites to be launched by the National Aeronautics and Space Administration (NASA) Earth Science Enterprise project. The Earth Observing System (EOS) AM-1 spacecraft, the first satellite of this new era, will produce in only six months as much data as NASA has collected to this date. As a consequence, the Earth Science Data and Information System (ESDIS) project is building high performance and highly costly parallel processing systems to address the real-time data production requirements. Together with the high performance front-end ingest and level 0 processing microcircuits developed in-house at the Goddard Space Flight Center’s (GSFC) Data Systems Technology Division (DSTD), adaptive computers present a possible alternative to traditional CPU-based systems to increase the performance while reducing the cost of satellite telemetry processing systems. The Adaptive Scientific Data Processing (ASDP) project has been investigating the use of adaptive computers in the implementation of space borne scientific data processing systems. An order of magnitude processing speed acceleration over high-end workstations has been demonstrated for both level 1 and level 3 algorithms. This paper discusses the use of adaptive computing in satellite telemetry processing systems, level 1 and beyond. Primarily, it describes the efforts and presents the results of two prototypes developed by the ASDP project. The limitations of the current state of the technology are discussed and the expected improvements to facilitate the adoption of adaptive computers are presented. Finally, future work of the ASDP project is discussed.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / In order to reduce the ground segment equipment cost for small space missions, the French national space center (CNES) had the need to develop a CCSDS down-link interface board for low telemetry rates (< 1.5 Mb/s). This board performs frame synchronization and Reed-Solomon decoding. An important part of this design was the Reed-Solomon decoder development. In order to maintain low recurrent cost for this board, this decoder was realized in FPGA technology. Reed-Solomon decoding function, interleaving function (from 1 to 5) and virtual fill management are included in the same component. All set-up parameters are software programmable via the PCI bus, data and status are also available via the PCI bus under windows NT operating system. This paper presents the main features of this board and an overview of the Reed-Solomon decoder development.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / The Central Control Facility at Eglin Air Force Base has acquired full intellectual rights to a single board telemetry card with device driver and test software. This card has an integrated IRIG 106 PCM decommutator, IRIG time clock and minimal PCM simulator capability using the latest in Field Programmable Gate Array technology. Eglin will offer this capability to the telemetry community as both open source hardware and software and solicit partnerships with both government and private industry for both open source and closed source for-profit products.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / Legacy telemetry systems, although widely deployed, are being severely taxed to support the high data rate requirements of advanced aircraft and missile platforms. Increasing data rates, in conjunction with loss of spectrum have created a need to use available spectrum more efficiently. In response to this, new modulation techniques have been developed which offer more data capacity in the same operating bandwidth. Demodulation of these new waveforms is a computationally challenging task, especially at high data rates. This paper describes the design, implementation and performance of a high-speed, multi-mode demodulator for the Advanced Range Telemetry (ARTM) program which meets these challenges.

FPGA systems can have a wide variety of applications within electrical engineering, product development, and prototyping. Their flexibility, low cost, and high performance have made it burst into the market with results that exceeded many expectations. National Instruments offers several software and hardware that integrate FPGA systems in their design and implementation. In this thesis work, a NI FPGA system is used along with LabVIEW myRIO 2014 software to run a graphical FPGA code, hence, identifying best practices that must be associated with using the software and the hardware of National Instruments FPGA interfaces and also compare different methods for programming, communication, and data conversion of the FPGA interfaces.

ITC/USA 2011 Conference Proceedings / The Forty-Seventh Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2011 / Bally's Las Vegas, Las Vegas, Nevada / This paper presents three telemetry techniques demonstrated on an affordable precision mortar that allowed the guidance, navigation, and control (GNC) system to be effectively analyzed. The first is a technique for the real-time integration and extraction of GPS data into a sensor telemetry stream. The second is a method for increasing telemetry bandwidth by saving a short period of high rate data and then broadcasting it over the rest of the flight test. Lastly, I present an on-board data storage implementation using a MicroSD card.

The aim of this work is to investigate the possibility to implement a configurable NPU (Network Processing Unit) in the next generation of Ericsson’s EMCAs (Ericsson Multi Core Architecture). The NPU is constructed so that it can be configured for either Ethernet or xIO-s, as either a transmitter or a receiver. The motive for doing the work is that many protocols have similar functions and there could be possible advantages to have a configurable protocol choice in future hardware. A model of a NPU will be created in SystemC using the TLM 2.0 interface. The model will be analyzed to evaluate its complexity regarding a possible modification to also make it configurable for CPRI. The result that is presented is that it would be possible to implement a configurable NPU in the future EMCAs. The result is based on the conclusion that the protocols use many similar functions and most of the blocks could be made configurable for use with different protocols. Configurable blocks would benefit a configurable NPU as it would require fewer resources than separate blocks for each protocol.

Embedded systems based on FPGAs frequently incorporate soft processors. The prevalence of soft processors in embedded systems is due to their flexibility and adaptability to the application. However, soft processors provide moderate performance compared to hard cores and custom logic, hence faster performing soft processors are desirable. Many soft processor architectures have been studied in the past including Vector processors and VLIWs. These architectures focus on regular applications in which it is possible to extract data and/or instruction level parallelism offline. However, applications with irregular parallelism only benefit marginally from such architectures. Targeting such applications, we investigate superscalar, out-of-order, and Runahead execution on FPGAs. Although these architectures have been investigated in the ASIC world, they have not been studied thoroughly for FPGA implementations. We start by investigating the challenges of implementing a typical inorder pipeline on FPGAs and propose effective solutions to shorten the processor critical path. We then show that superscalar processing is undesirable on FPGAs as it leads to low clock frequency and high area cost due to wide datapaths. Accordingly, we focus on investigating and proposing FPGA-friendly OoO and Runahead soft processors. We propose FPGA-friendly alternatives for various mechanisms and components used in OoO execution. We introduce CFC, a novel copy-free checkpointing which exploits FPGA block RAMs for fast and dense storage. Using CFC, we propose an FPGA-friendly register renamer and investigate the design and implementation of instruction schedulers on FPGAs. We then investigate Runahead execution and introduce NCOR, an FPGA-friendly non-blocking cache tailored for FPGAs. NCOR removes CAM-based structures used in conventional designs and achieves the high clock frequency of 278 MHz. Finally, we introduce SPREX, a complete Runahead soft core incorporating CFC and NCOR. Compared to Nios~II, SPREX provides as much as 38% higher performance for applications with irregular data-level parallelism with minimal area overhead.

Early closure to functional correctness of the final chip has become a crucial success factor in the semiconductor industry. In this context, the tedious task of functional debugging poses a significant bottleneck in modern electronic design processes, where new problems related to debugging are constantly introduced and predominantly performed manually. This dissertation proposes methodologies that address two emerging debugging problems in modern design flows. First, it proposes a novel and automated triage framework for Register-Transfer-Level (RTL) debugging. The proposed framework employs clustering techniques to automate the grouping of a plethora of failures that occur during regression verification. Experiments demonstrate accuracy improvements of up to 40% compared to existing triage methodologies. Next, it introduces new techniques for Field Programmable Gate Array (FPGA) debugging that leverage reconfigurability to allow debugging to operate without iterative executions of computationally-intensive design re-synthesis tools. Experiments demonstrate productivity improvements of up to 30 x vs. conventional approaches.