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This thesis introduces a new approach to compilation for FPGAs, which we call direct synthesis. We take a technology-mapped circuit netlist and directly map it into a pre-placed and routed FPGA overlay. Solving this problem may help to address the increasing portion of compile time that is attributed to placement and routing, and the tremendous amount of area and energy consumed by the highly flexible FPGA routing network. This thesis presents a direct synthesis algorithm and an algorithm for generating the pre-placed and routed FPGA overlays. Using the direct synthesis flow which we have designed, we can successfully map circuits less than 100 BLEs in size, after modest modi cations to the architecture of the FPGA overlay circuit. While we show that direct synthesis problem is challenging, further architectural modi cations are proposed which can allow the direct synthesis of larger circuits to succeed.

This thesis introduces a new approach to compilation for FPGAs, which we call direct synthesis. We take a technology-mapped circuit netlist and directly map it into a pre-placed and routed FPGA overlay. Solving this problem may help to address the increasing portion of compile time that is attributed to placement and routing, and the tremendous amount of area and energy consumed by the highly flexible FPGA routing network. This thesis presents a direct synthesis algorithm and an algorithm for generating the pre-placed and routed FPGA overlays. Using the direct synthesis flow which we have designed, we can successfully map circuits less than 100 BLEs in size, after modest modi cations to the architecture of the FPGA overlay circuit. While we show that direct synthesis problem is challenging, further architectural modi cations are proposed which can allow the direct synthesis of larger circuits to succeed.

To efficiently capture signal events when performing analog measurements, a competent toolbox is required. In this master thesis, a system for frequency domain triggering is designed and implemented. The implemented system provides advanced frequency domain trigger conditions, in order to ease the capture of a desired signal event. A real-time 1024-point pipelined feedforward FFT-core is implemented to transform the signal from the time domain to the frequency domain. The system is designed and synthesized for a Virtex-6 FPGA (XC6VLX240T) and is integrated into SP Devices’ digitizer ADQ1600. The implemented system is able to handle a continuous stream of 1.6GS/s at 16-bit. A small software API is developed that provides runtime configuration of the Triggering conditions.

The majority of modern high performance computing systems have employed on-chip multi-processors. As the number of on-chip cores soars, the traditional non- scalable communication infrastructures, commonly observed as shared buses or cross- bars, no longer accommodate the increasing communication demand by the modern multi-core chips. The newly emerging Network-On-Chip (NoC) interconnection scheme has provided a scalable, robust and power-efficient solution that also satisfies the requirements on both bandwidth and latency. A tool that enables swift exploration of the vast NoC design space is then in great demand to meet the stiff time pressure over research and development. Based on the work of AcENoCs, an NoC simulator designed on the basis of software and hardware codesign seeking for a large simulatable network size, the SPAcENoCs (Scalable Platform for FPGA Accelerated Emulator of NoCs) employs the Time-Division Multiplexing (TDM) techniques to implement a simulator for even larger NoCs without sacrificing simulation speed and cycle accuracy which have been highlighted in the work of AcENoCs. This paper will focus on re-organization of the given software/hardware codesigned frameworks so that the TDM techniques may be applied. While both frameworks require re-design, the major efforts involve re- construction of the hardware framework by adding data buffers and affiliated logic to ensure the data generated in different time divisions are properly preserved and trans- mitted. Various design tradeoffs over hardware budget and simulation performance are also discussed and attempted in this paper. During the development process, the techniques of device virtualization and generic programming are introduced to overcome the verification challenges that are commonly seen in software/hardware codesigned systems. The synthesis results of various design options suggested that the simulation of a 9 × 6 network, more than twice the size of largest applicable size in AcENoCs, can be accommodated by the device. Based on the simulation result of AcENoCs, the estimated speedup of SPAcENoCs over software simulator for the 9 × 6 NoC is around 28-94X, twice the one achieved by AcENoCs in a smaller network.

This thesis describes the implementation of the physical layer for an experimental low-power wireless communication device. The system utilizes differential coherent correlation and threshold-based detection to produce a robust random-access packet-based communications protocol. Prior to implementing the system in hardware, the detection algorithm was rigorously simulated with a software model in C. The simulations revealed the tradeoffs between the packet miss performance and different system parameters such as input bit precision and threshold value. Having determined a suitable configuration, the detection algorithm was implemented on an FPGA platform. The focus of the FPGA design was on throughput and resource utilization. The final system utilizes approximately 6% of the slices available on a Xilinx Virtex II XC2V8000 FPGA and has a throughput of about 5 MChips/Second.

Made available in DSpace on 2013-08-07T18:42:22Z (GMT). No. of bitstreams: 1 000447663-Texto+Completo-0.pdf: 3152066 bytes, checksum: ada0593d3cfeecc7c99152d88798658e (MD5) Previous issue date: 2010 / Arithmetic circuits are a fundamental part of digital systems, since every piece of information processed by them must first be encoded as numbers, and arithmetic is the ultimate way to systematically manipulate numbers. There exists a large number of available number encoding schemes, but three of these stand as useful in most situations: unsigned, integer and floating point. The first two are simpler and more universal, but some applications do require the recourse to the extended range of values, and the increased precision of floating point representations. Although the use of floating point hardware in FPGAs has long been considered unfeasible or relegated to use only in expensive devices and platforms, this is no longer the case. This work describes the design process, the implementation and a preliminary evaluation of single-precision floating point hardware units for an instance of the MIPS processor architecture. It explores several fully-fledged implementations that have the form of strongly coupled coprocessors. These coprocessors take as little room as 4% of a medium-sized FPGA, while the processor CPU may take only 3% of the same device. The space exploration process described here values area, performance and power metrics and considers variations on the choice of synthesis tool, floating point unit generation method and architectural issues such as clocking schemes. The conducted experiments show reductions of more than 20 times in clock cycles count for typical floating point application modules, when compared to the use of software-emulated floating point processing. / Circuitos aritméticos são parte fundamental de sistemas digitais, uma vez que cada porção de informação processada por estes deve ter sido codificada previamente sob a forma de números, e que a aritmética é a forma por excelência de proceder à manipulação sistemática de números. Existe uma grande quantidade de esquemas de codificação usados em sistemas digitais, mas três formas de representação se sobressaem por serem usadas na maioria maciça das situações: números sem sinal, números inteiros e a representação de ponto flutuante. Os dois primeiros são mais simples e mais universais, mas algumas aplicações exigem o recurso à faixa estendida de valores e à precisão incrementada de representações de ponto flutuante. Embora o uso de hardware de ponto flutuante em FPGAs tenha sido por muito tempo considerado inviável ou relegado ao uso apenas em dispositivos e plataformas de alto custo, esta não é mais a situação atual. Este trabalho descreve o processo de projeto, a implementação física e uma avaliação preliminar de unidades de processamento de ponto flutuante de precisão simples em hardware para uma arquitetura de processador MIPS. Exploram-se várias implementações completas que têm a forma de coprocessadores fortemente acoplados. Estes coprocessadores ocupam apenas 4% de um FPGA de tamanho médio, enquanto o processador em si ocupa 3% do mesmo dispositivo. O processo de exploração do espaço de soluções de projeto descrito aqui considera as figuras de mérito área, desempenho e potência e considera variações na escolha da ferramenta de síntese, do método de geração a unidade de ponto flutuante e questões arquiteturais tais como estratégias de uso de relógios. Os experimentos conduzidos mostram reduções de mais de 20 vezes na contagem do número de ciclos de relógio do processador, para módulos de aplicação típicos que usam ponto flutuante de forma intensiva, quando comparado com processamento de representações de ponto flutuante emulado em software.

This thesis describes the development of an eddy current instrument and its application in detecting early-stage pitting corrosion. Eddy current testing has previously been used in Non-Destructive Testing (NDT) applications detecting large defects, like cracks. However, the challenge of detecting corrosion pits of less than 1mm³ remains unaddressed. This research involved the design of a Field Programmable Gate Array (FPGA)-based eddy current instrument, and the design and modelling of a novel differential electromagnetic sensor. The FPGA provided accurate synchronisation among the major electronic components. The firmware developed as part of this research allowed for exact interfacing to A/D and D/A converters, performed a real-time demodulation and signal generation, the instrument also supported a multi-frequency eddy current application. The firmware showed promising end-results in terms of sensitivity and stability in relation to pitting corrosion detection. In summary, this instrument offered significant improvement in sensitivity; the size of corrosion detected is improved more than 10 per cent compared to the previously reported, which enabled the detection of pits smaller than 1 mm³. For the sensor probe, a novel differential sensor was proposed to minimise the background signal for plate scanning and improve the sensitivity. The designed probe has an advantageous feature: the sensor response can be analysed using a closed form analytical solution.