FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA. Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA. The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated. All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs. Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

In order to accelerate logic simulation, it is highly beneficial to simulate the circuit design on FPGA hardware. However, limited hardware resources on FPGAs prevent large designs from being implemented on a single FPGA. Hence there is a need to partition the design and simulate it on a multi-FPGA platform. In contrast to existing FPGA-based post-synthesis partitioning approaches which first completely flatten the circuit and then possibly perform bottom-up clustering, we perform a selective top-down flattening and thereby avoid the potential netlist blowup. This also allows us to preserve the design hierarchy to guide the partitioning and to make subsequent debugging easier. Our approach analyzes the hierarchical design and selectively flattens instances using two metrics based on slack. The resulting partially flattened netlist is converted to a hypergraph, partitioned using a public domain partitioner (hMetis), and reconverted back to a plurality of FPGA netlists, one for each FPGA of the FPGA-based accelerated logic simulation platform. We compare our approach with a partitioning approach that operates on a completely flattened netlist. Static timing analysis was performed for both approaches, and over 15 examples from the OpenCores project, our approach yields a 52% logic simulation speedup and about 0.74x runtime for the entire flow, compared to the completely flat approach. The entire tool chain of our approach is automated in an end-to-end flow from hierarchy extraction, selective flattening, partitioning, and netlist reconstruction. Compared to an existing method which also performs slack-based partitioning of a hierarchical netlist, we obtain a 35% simulation speedup.

L'enregistrement extracellulaire d'activité électrique est une technique très répandue en neurosciences, mais son application aux îlots pancréatiques et cellules bêta n'est que très récente. La facilité d'utilisation des MEAs (Microelectrode Arrays, Matrices de Microélectrodes) a ouvert de nouvelles perspectives à l'électrophysiologie des cellules bêta, dont des méthodes de criblage en clinique ou des approches biocapteur pour le pancréas artificiel. Cette thèse contribue à la conception et la caractérisation d'un biocapteur hybride composé de cellules pancréatiques cultivées sur un MEA et d'un système électronique de traitement du signal. Le système ainsi réalisé est le fruit de collaborations et projets pluridisciplinaires menés à l'IMS (groupe bioélectronique), en partenariat avec le CBMN (biologie cellulaire et biocapteurs), tous deux au sein de l'Université de Bordeaux. Les projets faisaient également appel au service d'endocrinologie des Hôpitaux Universitaires de Bordeaux, Montpellier, Grenoble et Genève.Les projets en question incluent:- ISLET-CHIP (ANR 2013-PRTS-0017), qui explore une méthode pour évaluer la qualité d'un greffon pancréatique destiné à des patients diabétiques de type I.- BIODIA (EU FEDER), qui caractérise la réponse électrique d'îlots à des stimuli de glucose, hormones et médicaments pour des applications de criblage, différentiation cellulaire, et en boucle-fermée.- DIAGLYC (Bourse régionale 2017 1R30 226), qui étudie l'utilisation du biocapteur hybride comme un capteur pour le pancréas artificiel.La thèse aborde le biocapteur dans ses aspects à la fois électronique et biologique, son intégration dans des expériences appliquées, et ses résultats expérimentaux. Elle s'intéresse également à la modélisation d'une boucle de régulation chez le patient diabétique de type I.D'abord, le système d'analyse électronique est décrit. Issue de l'équipe Elibio, elle réalise acquisition multicanaux et traitement du signal numérique. Elle est construite autour d'un FPGA (Field Programmable Gate Array) qui rend son architecture de calcul polyvalente et évolutive. Elle est capable de mesurer, afficher, et enregistrer des données multicanaux. Le calcul embarqué est optimisé pour de faibles latences de calcul, compatibles avec des applications en boucle fermée. La thèse décrit ses algorithmes de traitement et son architecture.Des résultats expérimentaux utilisant le système et ses algorithmes sont ensuite montrés pour illustrer la réponse des îlots à des stimuli de glucose, médicaments et hormones. L'activité des îlots est quantifiée en analysant leurs APs (Action Potentials, Potentiels d'Action), et plus notoirement leurs SPs (Slow Potentials, Potentiels Lents), une nouvelle signature électrique exclusivement mesurée sur les îlots pancréatiques. Ces mesures, en régimes statique et dynamique, contribuent non seulement à caractériser la réponse du biocapteur, mais aussi à mettre en évidence les algorithmes internes des îlots de Langerhans.Enfin, des approches pour l'intégration du biocapteur dans un pancréas artificiel sont étudiées. Les réponses au glucose et aux hormones sont modélisées et simulées dans un modèle des interactions glucose-insuline dans le corps entier. Ce concept est novateur dans le sens où le capteur en charge de mesurer le besoin d'insuline n'est pas seulement sensible au glucose, mais aussi aux hormones présentes dans le sang. / Extracellular recording of electrical activity is a widespread technique in neurosciences, but only recently has it been applied to pancreatic islets and beta cells. The ease of use of Microelectrode Arrays (MEAs) has opened new perspectives for the electrophysiology of pancreatic cells, including screening methods for clinics and biosensor approaches for the artificial pancreas. This thesis is a contribution to the design and characterization of a hybrid biosensor composed of pancreatic cells cultured on an MEA and dedicated processing electronics. This device is the product of multi-disciplinary projects conducted at IMS (Bioelectronics group), partnered with CBMN (Cell biology and Biosensors team), both at the University of Bordeaux. Projects also involved the endocrinology service of university hospitals in Bordeaux, Montpellier, Grenoble, and Geneva.The covered projects include:- ISLET-CHIP (French ANR 2013-PRTS-0017), investigating a method of evaluating the quality of a preparation prior to its transplantation in type-I diabetic patients.- BIODIA (EU FEDER), characterizing islet electrical response to glucose, hormone, and drug stimuli for screening, cell differentiation, and closed-loop approaches.- DIAGLYC (French regional grant 2017 1R30 226), investigating the use of the hybrid biosensor as an artificial pancreas front-end sensor.The thesis tackles the biosensor in both its electronic and biological aspects, its integration in applicative experimental setups, and experimental results. It also addresses the modeling of a closed regulation loop for type-I diabetic patients.First, the electronic processing platform is described. It is a custom board performing multichannel acquisition and digital signal processing. It is built around an FPGA (Field Programmable Gate Array) that makes its processing architecture versatile and evolutive. It is capable of measuring, displaying and storing multichannel data. Computation was optimized for low-processing latencies compatible with closed-loop configurations. Both its processing algorithms and architecture are detailed.Then, experimental results using this system and its algorithms are shown to illustrate islet response to glucose, drug, and hormone stimuli. Islet activity is quantified by analyzing Action Potentials (APs), and more importantly Slow Potentials (SPs), a novel electrical signature exclusively measured on pancreatic islets. These measurements in both steady state and dynamic regime help characterize the biosensor response, but also shed light on the endogenous algorithms of islets of Langerhans.Finally, approaches for integrating the biosensor in an artificial pancreas are investigated. The measured glucose and hormone responses are modeled and simulated in a full-body glucose-insulin system. This concept is novel in that the sensor in charge of measuring insulin demand in the body is not only sensitive to glucose, but also to blood hormones.

Made available in DSpace on 2014-12-17T14:55:44Z (GMT). No. of bitstreams: 1 AlanPOS_DISSERT.pdf: 1600832 bytes, checksum: d14cb41b3377752326e77580d9b32dba (MD5) Previous issue date: 2010-02-19 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / Blind Source Separation (BSS) refers to the problem of estimate original signals from observed linear mixtures with no knowledge about the sources or the mixing process. Independent Component Analysis (ICA) is a technique mainly applied to BSS problem and from the algorithms that implement this technique, FastICA is a high performance iterative algorithm of low computacional cost that uses nongaussianity measures based on high order statistics to estimate the original sources. The great number of applications where ICA has been found useful reects the need of the implementation of this technique in hardware and the natural paralelism of FastICA favors the implementation of this algorithm on digital hardware. This work proposes the implementation of FastICA on a reconfigurable hardware platform for the viability of it's use in blind source separation problems, more specifically in a hardware prototype embedded in a Field Programmable Gate Array (FPGA) board for the monitoring of beds in hospital environments. The implementations will be carried out by Simulink models and it's synthesizing will be done through the DSP Builder software from Altera Corporation. / A Separa??o Cega Fontes (BSS) refere-se ao problema de estimar sinais originais a partir de misturas lineares observadas sem nenhum tipo de conhecimento acerca das fontes ou do processo de mistura. A An?lise de Componentes Independentes (ICA) ? uma t?cnica aplicada principalmente ao problema do BSS e dentre os algor?tmos que implementam essa t?cnica, o FastICA ? um algor?tmo iterativo de alto desempenho e de baixo custo computacional que utiliza medidas de n?o-gaussianidade baseadas em estat?stica de alta ordem para estimar as fontes originais. O grande n?mero de aplica??es onde ICA se mostra ?til reflete a necessidade da implementa??o dessa t?cnica em hardware e o paralelismo natural do FastICA favorece a implementa??o desse algor?tmo em plataforma de hardware digital. Este trabalho prop?e a implementa??o do FastICA em uma plataforma de hardware reconfigur?vel para a viabiliza??o de sua utiliza??o em problemas de separa??o cega de fontes, mais especificamente em um prot?tipo de hardware embarcado em uma placa Field Programmable Gate Array (FPGA) para a monitora??o de leitos em ambientes hospitalares. As implementa??es ser?o realizadas atrav?s de modelos em Simulink e a sintetiza??o dos mesmos ser? feita com o aux?lio do software DSP Builder da Altera Corporation.

Esse trabalho tem por objetivo descrever o desenvolvimento e os atuais resultados do protótipo dataflow PIFLOW, um processador baseado no modelo de dataflow dinâmico, inspirado na Maquina Dataflow de Manchester e desenvolvido no Instituto de Física de São Carlos, da Universidade de São Paulo. Esse protótipo foi capaz de oferecer speedups muito próximos do ideal, a partir de programas que possuem grande grau de paralelismo, apresentando o grande potencial deste modelo - já bastante estudado no decorrer das últimas décadas - em oferecer desempenho superior ao de processadores sequenciais comerciais modernos. / The aim of this work is to describe the development and the current results of the PIFLOW dataflow prototype, a processor based on the dynamic dataflow model of execution, inspired by the Manchester Dataflow Machine and developed in the Instituto de Física de São Carlos, Universidade de São Paulo. This prototype shows speedups very close to the ideal case, when executing programs with a high degree of parallelism, showing the dataflow model potential, which has been extensibly analysed in the last decades, to offer higher performance when compared to commercial modern sequential processors.

Neste trabalho, é apresentado o desenvolvimento de um IP de rede Ethernet com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. O IPC foi adaptado do projeto Ethernet_tri_mode, e é capaz de transferir dados a velocidades de 1000, 100 e 10 Mbps. O desenvolvimento envolveu a adaptação do código para atingir os requisitos do projeto, feito segundo as diretrizes do CIERMag de manter todo o código em VHDL. Além disso, foi implementada uma interface de comunicação com o processador Nios II para tornar possível a configuração do sistema, bem como a transferência de dados através de um software sendo executado no processador. O IPC Ethernet foi projetado para ser aplicado no espectrômetro digital em desenvolvimento pelo CIERMag e teve como compromissos a baixa utilização de recursos lógicos do FPGA e, ao mesmo tempo, a disponibilização de uma alta taxa de transferência de dados para o espectrômetro. Como ferramenta de desenvolvimento, foi utilizada a plataforma Quartus II cujo fornecedor é a Altera. Já os testes em placa foram realizados em um kit de desenvolvimento DE3-150 da Terasic, o qual utiliza uma FPGA Stratix III, também da Altera. Com o intuito de testar e validar o sistema, foi desenvolvido um software para o processador Nios II capaz de receber e enviar dados através do IPC e com inteligência para responder pedidos do tipo ARP e PING. O subsistema de Gigabit Ethernet desenvolvido aqui já incorpora a versão corrente do Espectrômetro Digital de RM do CIERMag. / In this work we expose the implementation of an Ethernet network core which interfaces to Avalon bus used along with the Nios II Altera processor. This core was adapted from the Ethernet_tri_mode project. It can transfer data at rates of 1000, 100 and 10 Mbps. The development involved the adaptation of the code to fullfil the project requirements, under the policy of the CIERMag to keep the whole coding in VHDL. Furthermore was implemented an interface to communicate with the Nios II processor to enable system configuration and data transfer through a software running on the processor. The core was projected to be applied with focus on the utilization of low FPGA logical resources with the availability of a high data transfer rate. It will be used in a digital spectrometer under development at the CIERMag. The Quartus II platform, supplied by Altera was used as the development tool. The tests on board where carried out on a DE3-150 development kit from Terasic, which has an FPGA Stratix III also from Altera. In order to test and validate the system, a software for the Nios II processor was developed, able to send and receive data via IPC and with intelligence to answer ARP and PING types requests. The developed Gigabit Ethernet subsystem is now part of the running version of the CIERMag Digital MR Spectrometer.

Neste trabalho são apresentados os resultados obtidos no desenvolvimento de uma unidade de controle para motores de combustão interna (UCM). A unidade foi desenvolvida com o intuito de facilitar os estudos de motores, por ser um sistema flexível e acessível. Para cálculos de rotinas de controle e acionamento de atuadores são utilizados, respectivamente, um microcontrolador e um FPGA, sendo que ambos são componentes de fácil obtenção e utilizados em placas de prototipagem encontradas no mercado (Arduino Due e Xula 2). O uso de um FPGA para executar o comando de atuadores se deve à alta velocidade de processamento, processamento paralelo e grande quantidade de portas digitais disponíveis, o que permite facilidade na expansão do sistema para comandos de múltiplos atuadores e o sincronismo desses com o sistema mecânico. O microcontrolador fica encarregado de executar as rotinas de cálculos que não exigem exato sincronismo, como rotinas de controle e comunicação com periféricos. A planta escolhida para ensaios da UCM é um motor ciclo Otto a álcool de 4 cilindros e 1.6 litros, com injeção multiponto. Ensaios foram realizados com o protótipo final e englobaram somente o controle do sistema de ignição do motor devido à facilidade de controle utilizando-se somente um parâmetro de entrada (velocidade) e devido ao controle de quantidade de combustível ser similar e utilizar as mesmas partes de código que o sistema de ignição. / In this work is presented the development of a flexible and accessible engine control unit for research purposes. For the calculations of the control routines and to drive the actuators synchronously, are used respectively, a microcontroller and an FPGA. The integrated circuits selected are easily accessible and are used in common prototyping boards found on the market (Arduino Due and Xula 2). The use of an FPGA to control the activation of the actuators is due the high speed, parallel processing and the large number of IOs, which allows the easy expansion of the system to drive more actuators, synchronized or not, with the mechanical system. The microcontroller calculates the routines that dont need an exact synchronism of the electronic system with the mechanical system, like control routines and communication tasks. The selected mechanical system for tests is a 1.6 Liter Otto engine with multipoint fuel injection and is powered with ethanol. Tests were conducted using the final board prototype only for the ignition system, because of the easy of control using a few parameters, and because ignition FPGAs code is almost the same used to drive fuel injection actuators.

A escassez de equipamentos e soluções à disposição das pessoas portadoras de necessidades especiais é evidente e, na maioria dos casos, não está entre as prioridades primárias dos governos, tanto nos países desenvolvidos como, e principalmente, nos subdesenvolvidos. O desenvolvimento de dispositivos a preços acessíveis é, desta forma, uma carência real. O alto custo de fabricação de dispositivos assistivos é oriundo da necessidade de se construí-los de forma personalizada o que geralmente utiliza o estado da arte de determinada tecnologia. Aglutinando então, tecnologias já difundidas com novas abordagens e ferramentas, foi implementado um dispositivo assistivo com um índice de \"personalização\" extremamente baixo e com custo acessível. O método GRAFCET como ferramenta de desenvolvimento, aliado a tecnologia FPGA, nas fases de prototipação e produção, mostram-se eficazes e de fácil aplicabilidade. Para essa finalidade foi desenvolvida uma ferramenta de conversão GRAFCET - Circuito Digital que facilita e torna possível não só na elaboração do esquema GRAFCET, mas principalmente possibilita antever semelhança com outras aplicações que não são facilmente visualizadas num primeiro momento, permitindo a sua simplificação. O dispositivo concebido, mostrou que, com pequenas modificações, é possível desenvolvê-los de forma que atenda não apenas um, mas vários portadores de necessidades especiais, viabilizando assim a diminuição dos custos de projeto, desenvolvimento e construção dos equipamentos que venham a atender estas pessoas, permitindo assim melhora significativa em sua qualidade de vida. / In all countries, particularly in underdeveloped ones, there are few equipment and solutions available to people with physical disabilities, whose needs hardly rank among the government\'s top priorities. Therefore, there is a real need to develop low cost equipment to people with disabilities. The high cost of production of assistive devices results from the necessity of building them in a customized way, generally employing some state-of-the-art technology. This work proposes using well known technologies as tools, in such a way to allow the design of assistive devices with a low degree of customization and, consequently, at low cost. Using GRAFCET as a development tool and FPGA technology have shown to be an effective and easily applicable approach during the phases of prototyping and production. We developed a tool that converts GRAFCET designs into a digital circuit. The tool makes it easier to develop GRAFCET schemes and highlights the similarities among different applications, which otherwise could pass unnoticed, resulting in simplified designs. With small modifications, the proposed device can meet the needs of several people with disabilities, resulting in lower design, development and building costs of equipment that can significantly improve their quality of life.

A computação reconfigurável tem se tornado cada vez mais importante em sistemas computacionais embarcados e de alto desempenho. Ela permite níveis de desempenho próximos aos obtidos com circuitos integrados de aplicação específica (ASIC), enquanto ainda mantém flexibilidade de projeto e implementação. No entanto, para programar eficientemente os dispositivos, é necessária experiência em desenvolvimento e domínio de linguagem de descrição de hardware (HDL), tais como VHDL ou Verilog. As técnicas empregadas na compilação em alto nível (por exemplo, a partir de programas em C) ainda possuem muitos pontos em aberto a serem resolvidos antes que se possa obter resultados eficientes. Muitos esforços em se obter um mapeamento direto de algoritmos em hardware se concentram em loops, uma vez que eles representam as regiões computacionalmente mais intensivas de muitos programas. Uma técnica particularmente útil para isto é a de loop pipelining, a qual geralmente é adaptada de técnicas de software pipelining. A aplicação dessas técnicas está fortemente relacionada ao escalonamento das instruções, o que frequentemente impede o uso otimizado dos recursos presentes nos FPGAs modernos. Esta tese descreve uma abordagem alternativa para o mapeamento direto de loops descritos em uma linguagem de alto nível para FPGAs. Diferentemente de outras abordagens, esta técnica não é proveniente das técnicas de software pipelining. Nas arquiteturas obtidas o controle das operações é distribuído, tornando desnecessária uma máquina de estados finitos para controlar a ordem das operações, o que permitiu a obtenção de implementações eficientes. A especificação de um bloco de hardware é feita por meio de uma linguagem de domínio específico (LALP), especialmente concebida para suportar a aplicação das técnicas. Embora a sintaxe da linguagem lembre C, ela contém certas construções que permitem intervenções do programador para garantir ou relaxar dependências de dados, conforme necessário, e assim otimizar o desempenho do hardware gerado / Reconfigurable computing is becoming increasingly important in embedded and high-performance computing systems. It allows performance levels close to the ones obtained with Application-Specific Integrated circuits (ASIC), while still keeping design and implementation flexibility. However, to efficiently program devices, one needs the expertise of hardware developers in order master hardware description languages (HDL) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Many efforts trying to achieve a direct of algorithms into hardware concentrate on loops since they represent the most computationally intensive regions of many application codes. A particularly useful technique for this purpose is loop pipelining, which is usually adapted from software pipelining techniques. The application of this technique is strongly related to instruction scheduling, whic often prevents an optimized use of the resources present in modern FPGAs. This thesis decribes an alternative approach to direct mapping loops described in high-level labguages onto FPGAs. Different from oyher approaches, this technique does not inherit from software pipelining techniques. The control is distributed over operations, thus a finite state machine is not necessary to control the order of operations, allowing efficient harware implementations. The specification of a hardware block is done by means of LALP, a domain specific language specially designed to help the application of the techniques. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardware

O aumento da complexidade dos sistemas embarcados e a necessidade de um desenvolvimento cada vez mais acelerado têm motivado o uso de modelos abstratos que possibilitem maior flexibilidade e reusabilidade. Para isso, faz-se necessária a aceitação das linguagens e perfis mais abstratos, como o MARTE. Neste trabalho, foi desenvolvida uma ferramenta para conversão de sistemas embarcados independente de plataforma (PIM) em sistemas de uma plataforma específica (PSM), denominada I2S (Independente to Specific). O I2S é totalmente acoplável a novos desenvolvimentos e necessidades do projetista, capaz de modelar representações gráficas de sistemas embarcados, usando componentes do MARTE e permitindo uma implementação final em tecnologia reconfigurável. A partir de um modelo independente de plataforma faz-se a conversão para o padrão de projeto SOPC-Builder da Altera e XPS da Xilinx, possibilitando a exploração do espaço de projeto nessas duas tecnologias de modo automático. O trabalho faz análise de sistemas convertidos em diversas configurações e traz resultados relevantes para a área que validam o uso da proposta, atendendo aos requisitos de projeto / The growing of embedded systems complexity and the want for a quicker development has motivated the use of abstract models that improves flexibility and reusability. To these objective, we searched for the most adequate languages and profiles, like MARTE. In this work we developed a tool for conversion from platform independent models (PIM) to platfom specific models (PSM), named I2S (Independent to Specific). The I2S is totally acceptable to new developments and necessities of the designer, to open up modelling graphic representations of embedded systems using MARTE components and doing implementation in reconfigurable technology. A platform independent model is converted to the pattern of Alteras SOPC-Builder and Xilinxs XPS, making possible the exploitation of the project space in theses two tecnologies automatically. The work does analysis of systems converted in different configurations and shows relevant results to the area that validate the use of the proposal, meeting the project requirements