Thèse numérisée par la Division de la gestion de documents et des archives de l'Université de Montréal.

This project is part of research funded by NASA Langley in field of Unmanned Aerial Vehicles (UAVs) and is based on past work conducted at Virginia Commonwealth University. Dr. Mark A. Motter of NASA Langley intends to use the new autopilot system to test aircraft with many control surfaces. The goal of this project is to port an existing UAV autopilot system that has more computing power than the previous generation system to allow for more advanced flight control algorithms.The steps taken to complete this project include choosing a new hardware platform, porting C flight control software from a MicroBlaze platform to a PowerPC platform, and developing FPGA based hardware to interface with external sensors. The Suzaku-V based system was shown to have much better computing performance than the previous system, and several successful test flights have proved the viability of the new autopilot system.

In embedded systems, modeling the performance of the candidate processor architectures is very important to enable the designer to estimate the capability of each architecture against the target application. Considering the large number of available embedded processors, the need has increased for building an infrastructure by which it is possible to estimate the performance of a given application on a given processor with a minimum of time and resources. This dissertation presents a framework that employs the softcore MicroBlaze processor as a reference architecture where FPGA-based profiling is implemented to extract the functional statistics that characterize the target application. Linear regression analysis is implemented for mapping the functional statistics of the target application to the performance of the candidate processor architecture. Hence, this approach does not require running the target application on each candidate processor; instead, it is run only on the reference processor which allows testing many processor architectures in very short time.

Many physical, biological, ecological and behavioral events occur at times and rates that are exponentially distributed. Modeling these systems requires simulators that can accurately generate a large quantity of exponentially distributed random numbers, which is a computationally intensive task. To improve the performance of these simulators, one approach is to move portions of the computationally inefficient simulation tasks from software to custom hardware implemented in Field Programmable Gate Arrays (FPGAs). In this work, we study efficient FPGA implementations of exponentially distributed random number generators to improve simulator performance. Our approach is to generate uniformly distributed random numbers using standard techniques and scale them using the inverse cumulative distribution function (CDF). Scaling is implemented by curve fitting piecewise linear, quadratic, cubic, and higher order functions to solve for the inverse CDF. As the complexity of the scaling function increases (in terms of order and the number of pieces), number accuracy increases and additional FPGA resources (logic cells and block RAMs) are consumed. We analyze these tradeoffs and show how a designer with particular accuracy requirements and FPGA resource constraints can implement an accurate and efficient exponentially distributed random number generator.

The thesis evaluates the viability of reducing power consumption of a contem- porary computer cluster by using more power-efficient hardware components. The cluster in question runs an Map-Reduce algorithm implementation and the worker nodes consist of either systems with an ARM CPU or systems which combine both an ARM CPU and an FPGA in a single package. The behavior of such cluster is discussed from both performance side as well as power consumption side. The text discusses the problems and peculiarities with the integration of an ARM-based and especially the combined ARM-FPGA-based systems into the Map-Reduce framework. The Map-Reduce framework performance itself is eval- uated to identify the gravest performance bottlenecks when using the framework in the environment with ARM systems. 1

Les convertisseurs statique à structure tension sont des éléments essentiels de nombreux systèmes d'électronique de puissance tels que les variateurs de vitesse des machines alternatives, les alimentations sans interruption et les filtres actifs. Les défaillances d’un convertisseur, qu’elles proviennent d’un des composants de puissance commandables ou d’un des capteurs mis en œuvre, conduisent à la perte du contrôle des courants de phase. Ces défaillances peuvent provoquer de graves dysfonctionnements du système, voire conduire à sa mise hors tension. Par conséquent, afin d'empêcher la propagation de défauts aux autres composants et assurer la continuité de service en présence de défaut, des méthodes efficaces et rapides de détection et de compensation de défauts doivent être mises en œuvre. Dans ces travaux de thèse nous avons étudié un convertisseur triphasé à structure tension "fault tolerant". Ce convertisseur assure la continuité de service, en mode normal, en présence de défauts éventuels d’un semi-conducteur ou d’un capteur de courant. Dans ces travaux, nous avons choisi comme cas d’application le filtre actif parallèle (FAP) triphasé afin de valider la continuité de service du convertisseur "fault tolerant" lors de défauts. Les résultats expérimentaux montrent les performances et l’efficacité du convertisseur "fault tolerant" proposé. Pour réduire autant que possible le temps de détection du défaut, nous avons ciblé un composant numérique de type FPGA (Field Programmable Gate Array). Nous avons également proposé dans ce mémoire un nouveau flot de conception et de prototypage dit "FPGA in the loop" qui permet de réduire le temps de développement. / Voltage source converters (VSC) are essential components of many power electronics systems such as variable speed AC machines, uninterrupted power supplies and active power filters. A sudden failure in one of the used power switches or the current sensors decreases system performances and leads to disconnect the system. Moreover, if the fault is not quickly detected and compensated, it can lead to hard failure. Hence, to reduce the failure rate and to prevent unscheduled shutdown, effective and fast fault detection and compensation schemes must be implemented. In this thesis work we have studied a fault tolerant VSC. This converter provides the continuity of service in the presence of a semiconductor or a current sensor fault. In this work, we have chosen the shunt active power filter application to validate the studied fault tolerant VSC performances. The experimental results confirms the satisfactory performances and efficiency of the proposed fault tolerant VSC. To minimize the fault detection time, we targeted a FPGA (Field Programmable Gate Array) component. We also proposed in this thesis a new methodology to design and prototype so-called “FPGA in the Loop” that will reduce development time of the digital controllers.

Master of Science / Department of Electrical and Computer Engineering / Dwight D. Day / Over the last several years, the use of Field Programmable Gate Arrays, or FPGAs, has become increasingly popular in the embedded systems field. However, FPGAs are typically used only as a coprocessor or dedicated DSP. This project proposes that an embedded system can realize a performance gain over a traditional microprocessor-based design and be made more flexible and extensible by using an FPGA as the primary processing device in the embedded system. Basing a design on an FPGA also allows new features to be much more rapidly developed and integrated into the system. This will be shown by designing an FPGA based embedded system for Surface Systems & Instruments’ Walking Profiler device. The system will include support for rotary encoders, an incline sensor for data collection, and an Ethernet protocol for communication with a Windows computer. The implementation of a sub sampling distance measuring algorithm will be used to demonstrate the tradeoffs between hardware, software, and development times.

The FITkit platform incorporates an embedded system which enables students to create and implement complex designs not only of software projects but also of hardware projects or complete applications. So it is very important to invent and implement methods that can be used for testing the system during its whole life cycle. This thesis is engaged in testing the FITkit. The first part of the thesis is dedicated to familiarizing with the FITkit and its whole architecture. Terminology description and analysis of the dilemmas in testing can be found in the next part of the thesis. Further follows description of methods and procedures for testing the FITkit platform. A part of the thesis is a design of a testing application and description of its practical realization.

In this master thesis some of the most promising existing frameworks and implementations of deep convolutional neural networks on multiprocessor system-on-chips (MPSoCs) are researched and evaluated. The thesis’ starting point was a previousthesis which evaluated possible deep learning models and frameworks for object detection on infra-red images conducted in the spring of 2018. In order to fit an existing deep convolutional neural network (DCNN) on a Multiple-Processor-System on Chip it needs modifications. Most DCNNs are trained on Graphic processing units (GPUs) with a bit width of 32 bit. This is not optimal for a platform with hard memory constraints such as the MPSoC which means it needs to be shortened. The optimal bit width depends on the network structure and requirements in terms of throughput and accuracy although most of the currently available object detection networks drop significantly when reduced below 6 bits width. After reducing the bit width, the network needs to be quantized and pruned for better memory usage. After quantization it can be implemented using one of many existing frameworks. This thesis focuses on Xilinx CHaiDNN and DNNWeaver V2 though it touches a little on revision, HLS4ML and DNNWeaver V1 as well. In conclusion the implementation of two network models on Xilinx Zynq UltraScale+ ZCU102 using CHaiDNN were evaluated. Conversion of existing network were done and quantization tested though not fully working. The results were a two to six times more power efficient implementation in comparison to GPU inference.

Afin de répondre à une complexité croissante des systèmes de calcul, de nouveaux paradigmes architecturaux basés sur des structures auto-adaptatives et auto-organisées sont à élaborer. Ces derniers doivent permettre la mise à disposition d’une puissance de calcul suffisante tout en bénéficiant d’une grande flexibilité et d’une grande adaptabilité, cela dans le but de répondre aux évolutions des traitements distribués caractérisant le contexte évolutif du fonctionnement des systèmes. Ces travaux de thèse proposent une nouvelle approche de conception des systèmes communicants, auto-organisés et auto-adaptatifs basés sur des noeuds de calcul reconfigurable. Autrement dit, ces travaux proposent un système matériel autonome et intelligent, capable de déployer et de redéployer ses modules de calcul, en temps réel et en fonction de la demande de traitement et de la puissance de calcul. L’aboutissement de ces travaux se traduit par la réalisation d’un Système Auto-organisé Reconfigurable (SAR) basé sur la technologie FPGA. L’architecture auto-adaptative proposée permet d’étudier l’impact des systèmes reconfigurables dans une structure distribuée et auto-organisée. Le système est réalisé pour étudier, à chaque niveau, les paramètres qui influencent les performances globales d’un réseau de calcul évolutif. L’étude de l’état de l’art a permis la mise en perspective et la formalisation des caractéristiques du concept d’auto-organisation matérielle proposé ainsi qu’une évaluation et une analyse de ces performances. Les résultats de ces travaux montrent la faisabilité d’un système complexe de calcul distribué dont l’intelligence repose sur les interactions des éléments reconfigurables le constituant / Increasing needs of computation power, flexibility and interoperability are making systems more and more difficult to integrate and to control. The high number of possible configurations, alternative design decisions or the integration of additional functionalities in a working system cannot be done only at the design stage any more. In this context, where the evolution of networked systems is extremely fast, different concepts are studied with the objective to provide more autonomy and more computing power. This work proposes a new approach for the utilization of reconfigurable hardware in a self-organised context. A concept and a working system are presented as Reconfigurable Self-Organised Systems (RSS). The proposed hardware architecture aims to study the impact of reconfigurable FPGA based systems in a self-organised networked environment and partial reconfiguration is used to implement hardware accelerators at runtime. The proposed system is designed to observe, at each level, the parameters that impact on the performances of the networked self-adaptive nodes. The results presented here aim to assess how reconfigurable computing can be efficiently used to design a complex networked computing system and the state of the art allowed to enlighten and formalise characteristics of the proposed self-organised hardware concept. Its evaluation and the analysis of its performances were possible using a custom board: the Potsdam Intelligent Camera System (PICSy). It is a complete implementation from the electronic board to the control application. To complete the work, measurements and observations allow analysis of this realisation and contribute to the common knowledge