Nuclear spectroscopy is an interdisciplinary subject of physics and electronics, which adopts state-of-the-art digital electronic technology and computer technology to analyze the information in ionizing radiation. The use of FPGAs shortens the development cycles of the digital circuit design and reduces system noise with compact electronics size. As a result, digital spectrometers with FPGAs are gaining popularity in research and industrial markets. The motivation behind this work was to replace conventional analog electronics with modern digital technology to provide an excellent energy resolution for different kinds of nuclear detectors and experiments. In this thesis, a SiPM-based scintillation detector is first designed based on the basic principles of ionizing radiation. The readout circuit of the detector is given in detail. Subsequently, a real-time DPP module is designed using the FPGA of Lattice. The system noise of the DPP is measured, compared, and analyzed after the hardware verification and implementation of digital algorithms to assess the capability of the DPP module. Afterward, digital pulse processing algorithms are investigated in detail to improve the performance of the designed digital module. The design and implementation of multipass moving average and trapezoidal filter are presented. The PZC and BLR are designed and implemented according to the analysis of the trapezoidal filter’s weakness to have a better energy resolution of the digital system. Algorithms are designed and implemented on a Simulink platform. Experimental results and analyses are provided at the end of this thesis. The acquired data are analyzed in real-time or by offline software. Spectra and resolutions are demonstrated of different detectors to evaluate the performance of digital module and algorithms implementation. The resolution of the scintillation detector can be obtained to 4.2%, which is almost the optimal value based on their datasheet. The implementations of digital algorithms are verified. Other applications are provided, such as coincidence and cosmic muons measurements.

Computer Vision (CV) has become omnipresent in our everyday life and it’s starting to see more and more use in the industry. This movement creates a demand for ever more performant systems to keep up with the increasing demands in manufacturing speed and autonomous behaviours. Such computer vision (CV) systems need to run complex algorithms at real-time speed and sometime even in energy constrained systems. Thus efficient implementation of these algorithms are a must. One of those algorithm is the lens rectification algorithm (also sometime called undistortion algorithm) that is often one of the first algorithm to be used to correct for multiple imperfection that can occur in a camera and lens system. This algorithm has been implemented on FieldProgramable Gate Arrays (FPGAs) in past work but they either relied heavily on Dynamic Random Access Memory (DRAM) or used a subset of the full lens distortion model used by OpenCV and restricted themselves to small distortion amounts by having access to only parts of the image at a time. This thesis aims to create an open-source, DRAM-free FPGA implementation of the OpenCV lens rectification model of this algorithm, using the full 12-parameter model and allowing the use of any parameter which, to our knowledge, has not yet been implemented. To do so, a hybrid programming approach was taken meaning that both Hardware Descriptive Languages and High-Level Synthesis were used to arrive at the final implementation. The final implementation achieves 1300 frames per second with a sub-millisecond latency at a resolution of 320x240 on grayscale images. / Databearbetning (CV) har blivit allestädes närvarande i vårt vardagliga liv och det börjar se mer och mer användning inom industrin. Denna rörelse skapar ett efterfrågan på allt mer prestandastarka system för att hålla jämna steg med den ökande efterfrågan på tillverkningshastighet och autonoma beteenden. Sådana databearbetningssystem (CV) måste köra komplexa algoritmer i realtid och ibland även i energibegränsade system. Effektiva implementeringar av dessa algoritmer är därför ett måste. En av dessa algoritmer är linsrätningsalgoritmen (ibland även kallad oavvändningsalgoritm) som ofta är en av de första algoritmerna som används för att korrigera för flera fel som kan uppstå i ett kamerasystem och linssystem. Denna algoritm har implementerats på FieldProgramable Gate Arrays (FPGAs) i andra dokument tidigare, men de har antingen starkt beroende på Dynamic Random Access Memory (DRAM) eller använt en delmängd av den fullständiga linsdistortionmodellen som används av OpenCV och begränsat sig till små distortioner genom att ha tillgång till endast delar av bilden åt gången. Denna artikel syftar till att skapa en öppen källkod, DRAM-fri FPGA-implementering av OpenCV-linsrätningsmodellen av denna algoritm, med hjälp av den fullständiga 12-parametermodellen och tillåter användning av vilken parameter som helst, vilket inte har gjorts tidigare. För att göra detta togs ett hybridprogrammeringsansats, vilket innebär att både hårdvarubeskrivningsspråk och högnivåsyntes användes för att nå den slutliga implementeringen. Den slutliga implementeringen uppnår 1300 bilder per sekund med en sub-millisekund latens vid en upplösning på 320x240 på gråskalabilder.

This project focused on creating a PCB prototype to work with KTH's newly purchased FPGAs. This PCB is meant to be used to expand the FPGA's IO, as it did not have enough LEDs or switches to be used in some courses at the Embedded Systems program at KTH. An original design for the PCBs existed before this thesis was started, but it needed to be developed to meet the new requirements. Several prototypes were developed by first designing the PCB in KiCad. The design in KiCad then formed the basis for the physical prototype, which was milled out before the components could be soldered. The final functional prototype was approximately the size of the FPGA board and was connected to it by the FPGA's GPIO extension pins. The result of this thesis was a prototype that fulfilled the requirements and was ready for production. / Detta projekt fokuserade utifrån att skapa en PCB prototyp för att fungera med KTH:s nya inköpta FPGAs. PCBn som skulle skapas är ämnad att användas till att utöka en FPGAs IO, eftersom den inte hade tillräckligt med LEDar och switchar för att kunna användas i vissa kurser i programmet inbyggda system på KTH. Det fanns en ursprunglig design för påbyggnadskortet innan detta projekt började, men den behövde utvecklas för att uppfylla de nya krav som ställdes. Flera prototypkonstruktioner togs fram genom att först designa PCBn i KiCad. Designen i KiCad låg sedan som grund för den fysiska prototypen vilken frästes ut innan komponenterna kunde lödas fast. Den slutgiltiga funktionella prototypen var ungefär samma storlek som FPGA-brädan och anslöts till den existerande brädans GPIO-pins. Resultatet var en prototyp som uppfyllde de krav som ställts och som var redo för produktion på en större skala.

<p>The Stressometer system is a measurement and control system used in cold rolling to improve the flatness of a metal strip. In order to achieve this goal the system employs a multiple input multiple output (MIMO) control system that has a considerable number of sensors and actuators. As a consequence the computational load on the Stressometer control system becomes very high if too advance functions are used. Simultaneously advances in rolling mill mechanical design makes it necessary to implement more complex functions in order for the Stressometer system to stay competitive. Most industrial players in this market considers improved computational power, for measurement, control and modeling applications, to be a key competitive factor. Accordingly there is a need to improve the computational power of the Stressometer system. Several different approaches towards this objective have been identified, e.g. exploiting hardware parallelism in modern general purpose and graphics processors.</p><p>Another approach is to implement different applications in FPGA-based hardware, either tailored to a specific problem or as a part of hardware/software co-design. Through the use of a hardware/software co-design approach the efficiency of the Stressometer system can be increased, lowering overall demand for processing power since the available resources can be exploited more fully. Hardware accelerated platforms can be used to increase the computational power of the Stressometer control system without the need for major changes in the existing hardware. Thus hardware upgrades can be as simple as connecting a cable to an accelerator platform while hardware/software co-design is used to find a suitable hardware/software partition, moving applications between software and hardware.</p><p>In order to determine whether this hardware/software co-design approach is realistic or not, the feasibility of implementing simulator, computational and control applications in FPGAbased hardware needs to be determined. This is accomplished by selecting two specific applications for a closer study, determining the feasibility of implementing a Stressometer measuring roll simulator and a parallel Cholesky algorithm in FPGA-based hardware.</p><p>Based on these studies this work has determined that the FPGA device technology is perfectly suitable for implementing both simulator and computational applications. The Stressometer measuring roll simulator was able to approximate the force and pulse signals of the Stressometer measuring roll at a relative modest resource consumption, only consuming 1747 slices and eight DSP slices. This while the parallel FPGA-based Cholesky component is able to provide performance in the range of GFLOP/s, exceeding the performance of the personal computer used for comparison in several simulations, although at a very high resource consumption. The result of this thesis, based on the two feasibility studies, indicates that it is possible to increase the processing power of the Stressometer control system using the FPGA device technology.</p>

The Stressometer system is a measurement and control system used in cold rolling to improve the flatness of a metal strip. In order to achieve this goal the system employs a multiple input multiple output (MIMO) control system that has a considerable number of sensors and actuators. As a consequence the computational load on the Stressometer control system becomes very high if too advance functions are used. Simultaneously advances in rolling mill mechanical design makes it necessary to implement more complex functions in order for the Stressometer system to stay competitive. Most industrial players in this market considers improved computational power, for measurement, control and modeling applications, to be a key competitive factor. Accordingly there is a need to improve the computational power of the Stressometer system. Several different approaches towards this objective have been identified, e.g. exploiting hardware parallelism in modern general purpose and graphics processors. Another approach is to implement different applications in FPGA-based hardware, either tailored to a specific problem or as a part of hardware/software co-design. Through the use of a hardware/software co-design approach the efficiency of the Stressometer system can be increased, lowering overall demand for processing power since the available resources can be exploited more fully. Hardware accelerated platforms can be used to increase the computational power of the Stressometer control system without the need for major changes in the existing hardware. Thus hardware upgrades can be as simple as connecting a cable to an accelerator platform while hardware/software co-design is used to find a suitable hardware/software partition, moving applications between software and hardware. In order to determine whether this hardware/software co-design approach is realistic or not, the feasibility of implementing simulator, computational and control applications in FPGAbased hardware needs to be determined. This is accomplished by selecting two specific applications for a closer study, determining the feasibility of implementing a Stressometer measuring roll simulator and a parallel Cholesky algorithm in FPGA-based hardware. Based on these studies this work has determined that the FPGA device technology is perfectly suitable for implementing both simulator and computational applications. The Stressometer measuring roll simulator was able to approximate the force and pulse signals of the Stressometer measuring roll at a relative modest resource consumption, only consuming 1747 slices and eight DSP slices. This while the parallel FPGA-based Cholesky component is able to provide performance in the range of GFLOP/s, exceeding the performance of the personal computer used for comparison in several simulations, although at a very high resource consumption. The result of this thesis, based on the two feasibility studies, indicates that it is possible to increase the processing power of the Stressometer control system using the FPGA device technology.

Specific emitter identification refers to the process of performing identification of radio frequency transmitters by exploiting unique variations in emitted signals, caused by hardware variations. In previous research, specific emitter identification was successfully performed on GSM handsets. However, no research has been done on the implementation of specific emitter identification of GSM handsets on an FPGA platform. This study focuses on feature extraction and identification algorithms, as well as the implementation of the identification algorithm on an FPGA. During this study, phase modulation error was used, as previous research indicated that phase modulation error is an effective feature set for identification purposes. As the implementation of a classification algorithm on an FPGA was required, a trade-off between complexity and feasibility needed to be made during the selection process. The artificial neural network was selected as the optimal classifier for implementation on an FPGA. The algorithm was first implemented in software and used as the basis for the design on an FPGA. A piece-wise linear approximation of a sigmoid function was used to approximate the activation function, where a look-up table was used to store the parameters. The off-line training of the artificial neural network was performed in software using the back-propagation gradient descent algorithm. Good results for the identification of GSM handsets on an FPGA were obtained, with a true acceptance ratio of 97.0%. This result is similar to the performance obtained in previous research performed in software. In this study, it was found that specific emitter identification of GSM handsets can be performed on an FPGA. Real-world applications for this technology include general cellular handset identification and access control. / MSc (Electrical and Electronic Engineering), North-West University, Potchefstroom Campus, 2015

Specific emitter identification refers to the process of performing identification of radio frequency transmitters by exploiting unique variations in emitted signals, caused by hardware variations. In previous research, specific emitter identification was successfully performed on GSM handsets. However, no research has been done on the implementation of specific emitter identification of GSM handsets on an FPGA platform. This study focuses on feature extraction and identification algorithms, as well as the implementation of the identification algorithm on an FPGA. During this study, phase modulation error was used, as previous research indicated that phase modulation error is an effective feature set for identification purposes. As the implementation of a classification algorithm on an FPGA was required, a trade-off between complexity and feasibility needed to be made during the selection process. The artificial neural network was selected as the optimal classifier for implementation on an FPGA. The algorithm was first implemented in software and used as the basis for the design on an FPGA. A piece-wise linear approximation of a sigmoid function was used to approximate the activation function, where a look-up table was used to store the parameters. The off-line training of the artificial neural network was performed in software using the back-propagation gradient descent algorithm. Good results for the identification of GSM handsets on an FPGA were obtained, with a true acceptance ratio of 97.0%. This result is similar to the performance obtained in previous research performed in software. In this study, it was found that specific emitter identification of GSM handsets can be performed on an FPGA. Real-world applications for this technology include general cellular handset identification and access control. / MSc (Electrical and Electronic Engineering), North-West University, Potchefstroom Campus, 2015

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Range Safety Systems are used for destruction of a vehicle should a malfunction cause the vehicle to veer off course. All vehicles launched into space require implementation of a Range Safety System. For years the IRIG receivers have been used with relatively good success. Unfortunately, the IRIG receivers do not provide a high level of security. High alphabet receivers were later developed for use on the big launchers (Atlas, Delta, Titan, etc) and the manned missions (Shuttle) to provide added security. With the IRIG based system, several problems have occurred resulting in the loss millions of dollars worth of equipment. Due to the problems that have occurred it has become apparent that there is a need for a more secure, low cost, type of range safety receiver. This paper describes the design and development of the prototype EFTS system. Mission critical parameters are discussed including selection of the encryption and forward error correction algorithms. Actual measured performance including message error rate characteristic is presented.

ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada / NASA's Remote Imaging System Acquisition (RISA) project has the goal of producing a single robust and space-efficient imaging system. This paper will show the progress of the current RISA project iteration, tasked with implementing a Inter-Integrated Circuit (I²C) communications controller on a radiation hardened Field Programmable Gate Array (FPGA), characterizing a liquid lens optical system, and adding a radiation hardened temperature sensor. The optical design focuses on small liquid lenses that can vary focal length with no moving parts. The chosen designs will allow this camera system to meet critical mission objectives and provide reliable service to NASA's astronauts.

ITC/USA 2007 Conference Proceedings / The Forty-Third Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2007 / Riviera Hotel & Convention Center, Las Vegas, Nevada / The deployment of networks has become ubiquitous in the avionics world, as they have opened the door to a rich suite of common and open hardware and software tools that provide greater functionality and interoperability. Unfortunately, a number of networked avionic and other related applications can be affected by vendor or application specific proprietary implementations. These “closed” implementations may reduce or eliminate the benefits of a standardized network, requiring the customization of the data acquisition system to allow it to properly operate with the other devices. This paper presents the approach that was recently employed for the development of a network interface module that can be quickly reconfigured to address the changing requirements of network applications, including monitoring of industry standard and proprietary networks, or providing the command and data interface to the data acquisition system itself. This reconfigurability of the module is shown in a review of four different specific applications.