The world of nano-science is an ever-changing field. Molecular Dynamics (MD) is a computational suite of tools that is useful for analyzing and predicting behaviors of substances on the molecular level. The nature of MD is such that only a few types of computations are repeated thousands or sometimes millions of times over. Even a small increase speedup or efficiency of an MD simulator can compound itself over the life of the simulation and have a positive and observable effect. This thesis is the end result of an attempted speedup of the MD problem. Two types of MD architectures are developed: a dynamic architecture that is able to change along with the computational demands of the system, and a static architecture that is configured in terms of processing elements to be best suited to a variety of computational demands. The efficiency, throughput, area, and speed of the dynamic and static architectures are presented, highlighting the improvement that the dynamic architecture presents in its ability to provide load balancing.

In this thesis, an approach is proposed for the design and implementation of a serial peripheral interface using Complex Programmable Logic Devices, (CPLD's). The focus of this research was to develop an effective Serial Peripheral Interface. The Serial Peripheral Interface, (SPI), created by Motorola is also known as Microwire, which is a trademark of National Semiconductor. The SPI is a full-duplex, synchronous, serial data link that enables communication between a host processor and peripherals. The Serial peripheral interface can be programmed in software or built strictly in hardware inside a microcontroller. However, Complex programmable logic devices offer a quicker and more customizable solution. This research investigated the Serial peripheral interface with respect to its implementation in a CPLD and the use of the Very High Speed Integrated Circuit Hardware Description language, (VHDL).

With the transistor density on an integrated circuit doubling every 18 months, Moore’s law seems likely to hold for another decade at least. This exponential growth in digital circuits has led to its increased complexity, better performance and is quickly getting less manageable for design engineers. To combat this complexity, CAD tools have been introduced and are still being continuously developed, which prove to be of great help in the digital industry. One of the technologies, that is rapidly evolving as an industry standard, is the Very High Speed Integrated Circuit Hardware Description Language, (VHDL), language. The VHDL standard language along with logic synthesis tools are used to implement complex digital systems in a timely manner. The increase in the number of specialist design consultants, with specific tools accompanied by their own libraries written in VHDL, makes it important for a designer to have an in-depth knowledge about the available synthesis tools and technologies in order to design a system in the most efficient and reliable manner. This research dealt with writing VHDL code in terms of hardware modeling, based on coding styles, in order to get optimum results. Furthermore, it dealt with the interpretation of VHDL code into equivalent optimized hardware implementations, which satisfy the constraints of a set of specifications. In order to obtain a better understanding of the different VHDL tools and their usefulness in different situations, a comparative analysis between Altera’s QuartusII and Xilinx’s ISE Webpack tools, was performed. The analysis compared their Graphics User Interface, VHDL Code Portability and VHDL Synthesis constraints. The analysis was performed by designing and implementing a screensaver circuit on an FPGA and displaying it on the VGA Monitor.

Laser Fault Injection (LFI) testing has been demonstrated to be a useful tool in the prediction of single event upset rates in microcircuits. In addition LFI has contributed to the basic understanding of the mechanisms that cause single event upsets. However, very little research has been performed on the viability of LFI as a tool for verifying fault tolerant designs incorporated in ASICs, FPGAs, microprocessors and embedded systems. Current fault tolerant design verification techniques such as simulation and test have several significant limitations that prevent the complete verification of a fault tolerant design. However, LFI possesses spatial, temporal and financial advantages related to its use, which are very beneficial. This thesis presents results of the fault tolerance verification tests that were performed using laser fault injection on a four-bit fault tolerant filter that was implemented in a commercial FPGA.

A Trusted Platform Module (TPM) is a security device included in most modern desktop and laptop computers. It helps keep the computing environment secure by isolating cryptographic functions and data from the CPU. A TPM is usually implemented with a small microcontroller which is near the main processor. In addition to a microcontroller, it may employ hardware acceleration to assist in cryptographic computations. When vulnerabilities are found, or new algorithms developed, TPMs become obsolete because the hardware accelerators cannot be upgraded. This thesis presents a proof of concept implementation of a TPM on an FPGA. By using an FPGA, the TPM gains the ability to be upgraded or have new cryptographic modules added. This new design easily fits on the Zynq FPGA used in this work, with room left over for additional functionality. We explore the feasibility of this approach, including the added cost of the FPGA, and the added benefits of reconfigurable hardware.

Braille, as a special written method of communication for the blind, has been globally accepted for years. It gives blind people another chance to learn and communicate more efficiently with the rest of the world. It also makes possible the translation of printed languages into a written language which is recognisable for blind people. Recently, Braille is experiencing a decreasing popularity due to the use of alternative technologies, like speech synthesis. However, as a form of literacy, Braille is still playing a significant role in the education of people with visual impairments. With the development of electronic technology, Braille turned out to be well suited to computer-aided production because of its coded forms. Software based text-to-Braille translation has been proved to be a successful solution in Assistive Technology (AT). However, the feasibility and advantages of the algorithm reconfiguration based on hardware implementation have rarely been substantially discussed. A hardware-based translation system with algorithm reconfiguration is able to supply greater throughput than a software-based system. Further, it is also expected as a single component integrated in a multi-functional Braille system on a chip. / Therefore, this thesis presents the development of a system for text-to-Braille translation implemented in hardware. Differing from most commercial methods, this translator is able to carry out the translation in hardware instead of using software. To find a particular translation algorithm which is suitable for a hardware-based solution, the history of, and previous contributions to Braille translation are introduced and discussed. It is concluded that Markov systems, a formal language theory, were highly suitable for application to hardware based Braille translation. Furthermore, the text-to-Braille algorithm is reconfigured to achieve parallel processing to accelerate the translation speed. Characteristics and advantages of Field Programmable Gate Arrays (FPGAs), and application of Very High Speed Integrated Circuit Hardware Description Language (VHDL) are introduced to explain how the translating algorithm can be transformed to hardware. Using a Xilinx hardware development platform, the algorithm for text-to-Braille translation is implemented and the structure of the translator is described hierarchically.

Packet broadcast networks are in widespread use in modern wireless communication systems. Medium access control is a key functionality within such technologies. A substantial research effort has been and continues to be invested into the study of existing protocols and the development of new and specialised ones. Academic researchers are restricted in their studies by an absence of suitable wireless MAC protocol development methods. This thesis describes an environment which allows rapid prototyping and evaluation of wireless medium access control protocols. The proposed design flow allows specification of the protocol using the specification and description language (SDL) formal description technique. A tool is presented to convert the SDL protocol description into a C++ model suitable for integration into both simulation and implementation environments. Simulations at various levels of abstraction are shown to be relevant at different stages of protocol design. Environments based on the Cinderella SDL simulator and the ns-2 network simulator have been developed which allow early functional verification, along with detailed and accurate performance analysis of protocols under development. A hardware platform is presented which allows implementation of protocols with flexibility in the hardware/software trade-off. Measurement facilities are integral to the hardware framework, and provide a means for accurate real-world feedback on protocol performance.

Modern high-performance digital signal processing (DSP) applications face constantly increasing performance requirements and are becoming increasingly challenging to develop and work with. In DSP paradigm, many researchers see potential in achieving algorithm speed-up by employing Field Programmable Gate Arrays (FPGAs) – reconfigurable hardware with parallelism feature. However, developing applications for FPGAs incur particular challenges on the development flow. This work proposes a scalable hybrid DSP system for performing high-performance signal processing applications. The system employs hybrid CPU + FPGA architecture of commercially available, off-the-shelf (COTS) FPGAs and central processing units (CPU) of personal computers. In this work an example implementation of a multi-channel cross-correlator is investigated and delivered using a new development paradigm. The correlator is implemented on the XD1000 development system using a high-level FPGA programming tool – Impulse CoDeveloper. Analysis of DSP application development in a hybrid CPU+FPGA system employing the high-level programming tool Impulse C is presented. Potential of the selected tool to deliver algorithm speed-ups is investigated using reference multi-channel correlator software. Particular attention is devoted to input/output (I/O) implementation, which is considered one of the most challenging problems in FPGA design development. This work delivers an I/O framework based on PCI Express interface for the proposed high-performance scalable DSP system. Using Stratix II GX PCI Express Development Board from Altera Corporation, a scalable and flexible communication approach for the multi-channel correlator is delivered. This framework can be adapted to perform other high-performance streaming DSP applications. The outcomes of this work are a multi-channel correlator developed in a reconfigurable environment with new design methodology and I/O framework with software control application. The outcomes are used to demonstrate the potential of implementing DSP applications in hybrid CPU + FPGA architecture and to discuss existing challenges and suggest possible solutions.

One particular application domain of interest for sensor networks is in the real-time processing of audio information for ecological research questions such as species identification. Real-time audio processing generally involves sophisticated signal processing algorithms and requires substantial computational power. As FPGAs increase in capacity and speed but decrease in cost and power consumption, they are now able to provide low-cost, high performance, energy efficient, flexible, and convenient implementations for a wide range of digital systems. This thesis uses the computational power and single-chip solution capabilities of FPGAs to implement a typical audio processing application for sensor networks onto an FPGA using software / hardware co-design approach, and then evaluate the usefulness of this approach. Some background on sensor networks, audio recognition, FPGAs, MicroBlaze and hardware / software co-design is firstly introduced. A few widely adopted feature extraction and pattern matching algorithms are also presented and compared. Several digital signal processing applications based on FPGAs are then reviewed and analyzed. Software / hardware co-design method is then employed to implement an example system. A bird call recognition system based on linear predictive cepstral coefficients and dynamic time warping algorithm is developed and verified on a PC. Then, a software-only solution for this bird call recognition system is implemented on an FPGA with embedded MicroBlaze processor in a Xilinx development board. By means of code profiling, the performance bottlenecks of the software-only solution are identified. Taking the profiling results and the complexity of the recognition algorithm into account, the dynamic time warping algorithm was mapped into custom FPGA hardware. Fast Simplex Links, which are intended specially for high-speed uni-directional transfers to and from the processor, were used to attach the custom hardware to MicroBlaze and pre-defined driver functions supplied by EDK enabled the communications between software and the custom hardware. The software-hardware implementation was then built after substituting custom hardware for software counterparts. The influence of memory assignments for performance is also investigated. External memory access is identified as a major bottleneck. By moving all code from external DRAM into internal BRAM, the system performance is increased by a factor of about 10. From the analysis and comparison of execution time, logic area, and energy consumption of various implementations, it is shown that the software-hardware implementation can speed up a software-only FPGA implementation up to 528 times, and achieves of the order of 20 times “time-area efficiency” and 40 times energy efficiency. Compared with the PC-based C implementation running with a 40 times faster clock rate, the improved software-hardware system runs only about 7 times slower and its performance can meet the real-time requirement to complete a recognition in under one second. In addition, the software / hardware co-design also significantly reduces the energy consumption associated with individual computations.

<p>Companies and authorities of today often handle large amount of data, not unusually with a restricted content which should be kept secret from outsiders. One way of accomplish this is to encrypt stored data in real time. For this a hardware solution is ideal since it can be independent, fast enough, and easily added to already existing systems.</p><p>This report is a starting point to achieve this with two of the most common mass storage standards SATA and SCSI in focus. It is based on the task to develop a FPGA based SATA controller and investigate the possibility to ”speak” SCSI with SATA devices.</p><p>The working process has involved theoretical studies, system design, test driven development using simulations and hardware tests and technical investigation.</p><p>The thesis resulted in a SCSI-to-SATA translation investigation pointing out difficulties and presenting a translation model. A SATA host was also implemented in VHDL on a Virtex-5 FPGA that can execute a number of SATA commands on different devices. Simulations performed shows that the total latency reaches one <em>μ</em>s/32 bits in the SATA host and that should not be much of a problem for most applications in a possible bridge solution. </p>