O consumo de energia é uma das questões mais importantes em sistemas embarcados. Estudos demonstram que neste tipo de sistema a cache é responsável por consumir a maior parte da energia fornecida ao processador. Na maioria dos processadores embarcados, os parâmetros de configuração da cache são fixos e não permitem mudanças após sua fabricação/síntese. Entretanto, este não é o cenário ideal, pois a configuração da cache pode não ser adequada para uma determinada aplicação, tendo como consequência menor desempenho na execução e consumo excessivo de energia. Neste contexto, este trabalho apresenta uma implementação em hardware, utilizando computação reconfigurável, capaz de reconfigurar automática, dinâmica e transparentemente a quantidade de ways e por consequência o tamanho da cache de dados do processador embarcado LEON3, de forma que a cache se adeque à aplicação em tempo de execução. Com esta técnica, espera-se melhorar o desempenho das aplicações e reduzir o consumo de energia do sistema. Os resultados dos experimentos demonstram que é possível reduzir em até 5% o consumo de energia das aplicações com degradação de apenas 0.1% de desempenho / Energy consumption is one of the most important issues in embedded systems. Studies have shown that in this type of system the cache consumes most of the power supplied to the processor. In most embedded processors, the cache configuration parameters are fixed and do not allow changes after manufacture/synthesis. However, this is not the ideal scenario, since the configuration of the cache may not be suitable for a particular application, resulting in lower performance and excessive energy consumption. In this context, this project proposes a hardware implementation, using reconfigurable computing, able to reconfigure the parameters of the LEON3 processor\'s cache in run-time improving applications performance and reducing the power consumption of the system. The result of the experiment shows it is possible to reduce the processor\'s power consumption up to 5% with only 0.1% degradation in performance

Au cours des dernières années, les drones civils sont devenus un outil intéressant dans la photographie aérienne et dans les travaux de photogrammétrie. Cela a poussé le LOEMI (Laboratoire d’Opto-Electronique, Métrologie et Instrumentation) de l'IGN (Institut National de l'Information Géographique et Forestière) de mettre au point une nouvelle caméra aérienne mieux adaptée pour l'exploitation photogrammétrique et métrologiques des images que les caméras grand public. Cette caméra est composée essentiellement d'un capteur CMOS ``global-shutter'', d'une centrale inertielle IMU, et d'un système sur puce (FPGA + 2 CPUs) pour la gestion de l'acquisition des images. Ce SoC/FPGA ouvre la porte à l'implémentation temps-réel des algorithmes de traitement d'image. Parmi les travaux futurs de l'IGN, on peut distinguer certaines applications qui nécessitent l'acquisition des images aériennes avec un temps d'exposition long, comme par exemple les prises de vue aériennes en bande spectrale étroite et les prises de vue aériennes de nuit. Ce type de prises de vue manifeste un flou de bougé dans les images dû aux mouvements erratiques du drone. Cette thèse consiste en l'implémentation dans la caméra légère de l'IGN d'un algorithme qui permet de remédier ce problème de flou de bougé. La première partie de ce travail a été consacrée au développement de la méthode qui consiste à acquérir plusieurs images avec un temps de pose court, puis utiliser un algorithme de traitement d'image afin de générer une image empilée finale avec l'équivalent d'un temps de pose long. Les paramètres des orientations correctes pour le ré-échantillonnage des images sont obtenus par l'estimation de la transformation géométrique entre la première image et la nième image à partir des points d'intérêts détectés par FAST dans la première image et les points homologues obtenus par corrélation dans les autres images accélérées par les capteurs inertiels intégrés à la caméra. Afin d'accélérer le traitement de calcul de notre algorithme, certaines phases sont accélérées en les implémentant dans le matériel (SoC/FPGA).Les résultats obtenus sur des jeux de tests acquis avec un drone type Copter 1B UAV et la caméra ultra-légère de l'IGN montrent que l'image finale empilée ne présente pas un flou de bougé. Les résultats de temps des différentes phases de l'algorithme montrent aussi que l'exécution de notre algorithme a un temps quasi-nulle. Un des sous-produits intéressants de ces travaux est la ré-étalonnage des capteurs IMU / In the recent years, the civilian UAVs (Unmanned Aerial Vehicles) have become an interesting tool in aerial photography and in photogrammetry. This led the LOEMI (Laboratoire d'Opto-électronique, de Métrologie et d'Instrumentation) team of IGN (Institut National de l'Information Géographique) to design an light-weight digital camera better adapted for exploiting photogrammetry and metrology applications than consumer cameras. This camera consists essentially of a CMOS ``global shutter'' sensor, an inertial measurement unit IMU, and a system on chip (FPGA + 2 CPUs) used originally to acquire image data from the sensor. This SoC/FPGA-based camera opens the door to implement in hardware some real-time image processing algorithms. Night-time surveys and narrow spectral band with imagery are one of the next applications targeted by IGN, this type of applications needs a long-exposure time imagery that usually exhibits a motion blur due to erratic movements of the UAV. This thesis consists in the implementation on the light-weight IGN camera of an alogirithm which makes it possible to remedy this problem of motion blur. The first part of this work was devoted to the development of the method which consists in acquiring several images with a short exposure time and then using an image processing algorithm in order to generate a stacked image with the equivalent of a long-exposure time. To obtain the correct parameters for the resampling of images, the presented method accurately estimates the geometrical relation between the first and the nth image, taking into account the internal parameters and thedistortion of the camera. Features are detected in the first image by the FAST detector, than homologous points on other images are obtained by template matching aided by the IMU sensors. In order to speed up the processing of our algorithm, some phases are accelerated by implementing them in the hardware (SoC / FPGA).The results obtained on real surveys show that the final stacked image does not present a motion blur. The time results of the different phases of the algorithm also show that the execution of the algorithm has a quasi-zero time. One of the interesting byproducts of this work is the recalibration of the IMU sensors

Les systèmes électroniques sont de plus en plus présents dans les sociétés modernes, on peut les retrouver sous des formes très variées, très simple comme le réveil au chevet du lit ou très complexe comme un satellite de télécommunication en orbite. De nos jours, la majorité de ces inventions reposent en partie sur des "systèmes sur puces" afin de parvenir à accomplir leurs fonction principale, à savoir nous simplifier notre quotidien.Toutefois, à cause de leur nature physique, ces systèmes peuvent subir des dysfonctionnements dûs aux environnements dans lesquels ils évoluent. Des phénomènes naturels peuvent provoquer des aléas susceptibles d'avoir des conséquences graves sur la sûreté de fonctionnement du système.Cette thèse étudie la fiabilité d'une classe spécifique de systèmes sur puce capables de se reconfigurer partiellement de manière dynamique. Nous explorons la possibilité d'utiliser leur capacité de reconfiguration dynamique partielle (RDP) pour durcir les applications sur FPGAs. Nous avons proposé l'utilisation des approches de sauvegarde et de restauration de contexte pour la tolérance contre les fautes transitoire. La RDP est utilisée pour la gestion de contexte des tâches matérielles de l'application reconfigurable, le recours à la RDP permet de réduire les modifications à apporter au système initial et la complexité du système résultant. Après identification des limitations de l'approche "Backward Error Recovery" sur les plateformes FPGAs à base de mémoire SRAM, nous proposons un nouveau algorithme de placement des ressources sur FPGA afin de minimiser les temps d'accès des opérations de sauvegarde et de restauration d'une tâche matérielle. L'évaluation de la fiabilité de notre approche est réalisée à travers une campagne d'injection de faute sur une plateforme de démonstration basée sur un FPGA Virtex-5 qui intègre le contrôleur de fiabilité et une application de chiffrement de données. / Electronic systems are a growing need in modern societies, they can be found in a variety of forms, simple as an Alarm Clock at the bedside or very complex as a telecommunications satellite into orbit. Today, the majority of these inventions are based mainly on "systems on chips", in order to achieve their primary function: simplify our daily lives.However, because of their physical nature, these systems can suffer from malfunctions due to the environments in which they operate. Natural phenomena can cause hazards which may have serious consequences on system dependability.This thesis focuses on a specific class of systems on chip which are able to reconfigure dynamically and partially and their reliability. We explore the possibility of using their partial dynamic reconfiguration capability (PDR) for hardening applications on FPGAs. We have proposed the use of checkpoint approaches and context restoration for tolerance against transient faults. PDR is used for managing the context of hardware tasks present on the application. the use of RDP reduces changes to the original system and therefore the complexity of the resulting system. After identifying the limitations of the "Backward Error Recovery" approach into SRAM-based FPGAs platforms, we propose a new resource placement algorithm on FPGA to minimize the access time needed by check-pointing and rolling back operations of hardware tasks. The evaluation of the overall reliability of our approach is achieved through fault injection campaign on demonstration platform running on a Virtex-5 that integrates our reliability controller and hosts a data encryption application.

NIALM (Non-Intrusive Load Monitoring) est une technologie innovante qui permet de suivre la consommation individuelle en énergie des différents appareils électriques dans un réseau électrique grâce à un seul point de mesure. Ainsi, l’installation et la maintenance du système est très simple. Cependant, le logiciel NIALM nécessite le développement d’algorithmes sophistiqués pour identifier la consommation de chaque appareil avec une bonne précision. Par conséquent, ces algorithmes complexes nécessitent une plate-forme d’exécution puissante et coûteuse. En réponse à ce problème, cette thèse propose un système NIALM innovant fonctionnant en temps réel et à faible coût. Ce système permet de dépasser certaines limites actuelles du NIALM grâce à une extraction d’informations supplémentaires sur les signatures électriques, une détection des transitions lentes et des appareils à multi-états grâce à deux nouvelles fonctions : un algorithme de détection d'événements CUSUM et une ventilation des sommes cumulées en se basant sur un algorithme génétique. La deuxième contribution importante est de proposer une méthodologie utilisant le modèle RPN (Reactive Process Network) pour développer le système NIALM dans un SoC (System on Chip) avec une accélération matérielle de type FPGA. Ce SoC permet ainsi l'exécution en parallèle dans le FPGA de processus de traitement de données avec des algorithmes complexes tout en satisfaisant les contraintes de temps. Les avantages de notre méthode sont : la capacité de développer une spécification exécutable, d’effectuer une exploration d'architecture, et d’obtenir rapidement un prototype du système NIALM à partir d’un même modèle applicatif. / In comparison to conventional smart meters, NIALM (Non-Intrusive Load Monitoring) is an innovative technology because it can monitor power usage on individual appliances in an electrical network using only one sensing node. Thus, setting up and maintaining the system is very simple because of the few of hardware elements. In contrast, the software of NIALM is often very complex and there is still the need in developing more complex algorithms to classify appliances more accurately. These complex algorithms of NIALM require to run on a powerful and expensive hardware platform. In order to overcome this problem, the first contribution of this thesis is to propose a low cost real-time innovative NIALM system to solve some limits of NIALM design by extracting more electrical signatures, detecting slow transition and multi-state appliances, and energy disaggregation in real-time. This is possible by using two new algorithms: CUSUM event detection algorithm and disaggregation based on Genetic Algorithm. Similar to complex DSP systems, a NIALM system contains both event control processes and data streaming processes. The second important contribution of this research is to propose a methodology based on RPN model (Reactive Process Network) to develop a complex NIALM system in SoC with FPGA acceleration. Such SoC allows running data streaming processes with complex algorithms and hard timing constraints in parallel in FPGA while other processes can run in processors. The advantages of our methodology are the ability to develop an executable specification to proceed to architecture exploration, and prototype the NIALM system quickly using the same application model.

The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concepts are analyzed and com- bined. On one side are reconfigurable virtual FPGAs. They are a flexible resource and fulfill the cloud characteristics at the price of security. But on the other side is a strong requirement for said security. To provide it, an immutable controller is embedded enabling a direct, confidential and secure transfer of clients’ configurations. This establishes a trustworthy compute space inside an untrusted cloud environment. Clients can securely transfer their sensitive data and algorithms without involving vulnerable software or a data center provider. This concept is implemented as a prototype. Based on it, necessary changes to current FPGAs are analyzed. To fully enable reconfigurable yet secure hardware in the cloud, a new hybrid architecture is required. / Das Geschäft mit dem Cloud Computing wächst Jahr für Jahr. Um mit der steigenden Nachfrage mitzuhalten und neue Angebote zu bieten, sind Betreiber von Rechenzentren immer auf der Suche nach neuen Architekturen. Eine davon sind FPGAs, rekonfigurierbare Hardware mit hoher Rechenleistung und Energieeffizienz. Aber manche Kunden können die ausgelagerten Rechenkapazitäten nicht nutzen. Nicht alle Beteiligten sind vertrauenswürdig und die komplexe Verwaltungssoftware ist anfällig für Sicherheitslücken. Daher können die sensiblen Daten dieser Kunden nicht ausreichend geschützt werden. In dieser Arbeit werden modernste Hardware, Cloud und Sicherheitskonzept analysiert und kombiniert. Auf der einen Seite sind virtuelle FPGAs. Sie sind eine flexible Ressource und haben Cloud Charakteristiken zum Preis der Sicherheit. Aber auf der anderen Seite steht ein hohes Sicherheitsbedürfnis. Um dieses zu bieten ist ein unveränderlicher Controller eingebettet und ermöglicht eine direkte, vertrauliche und sichere Übertragung der Konfigurationen der Kunden. Das etabliert eine vertrauenswürdige Rechenumgebung in einer nicht vertrauenswürdigen Cloud Umgebung. Kunden können sicher ihre sensiblen Daten und Algorithmen übertragen ohne verwundbare Software zu nutzen oder den Betreiber des Rechenzentrums einzubeziehen. Dieses Konzept ist als Prototyp implementiert. Darauf basierend werden nötige Änderungen von modernen FPGAs analysiert. Um in vollem Umfang eine rekonfigurierbare aber dennoch sichere Hardware in der Cloud zu ermöglichen, wird eine neue hybride Architektur benötigt.

Les fonctions non clonables physiquement, appelées PUF (Physically Unclonable Functions), représentent une technologie innovante qui permet de résoudre certains problèmes de sécurité et d’identification. Comme pour les empreintes humaines, les PUF permettent de différencier des circuits électroniques car chaque exemplaire produit une signature unique. Ces fonctions peuvent être utilisées pour des applications telles que l’authentification et la génération de clés cryptographiques. La propriété principale que l’on cherche à obtenir avec les PUF est la génération d’une réponse unique qui varie de façon aléatoire d’un circuit à un autre, sans la possibilité de la prédire. Une autre propriété de ces PUF est de toujours reproduire, quel que soit la variation de l’environnement de test, la même réponse à un même défi d’entrée. En plus, une fonction PUF doit être sécurisée contre les attaques qui permettraient de révéler sa réponse. Dans cette thèse, nous nous intéressons aux PUF en silicium profitant des variations inhérentes aux technologies de fabrication des circuits intégrés CMOS. Nous présentons les principales architectures de PUF, leurs propriétés, et les techniques mises en œuvre pour les utiliser dans des applications de sécurité. Nous présentons d’abord deux nouvelles structures de PUF. La première structure appelée “Loop PUF” est basée sur des chaînes d’éléments à retard contrôlés. Elle consiste à comparer les délais de chaînes à retard identiques qui sont mises en série. Les points forts de cette structure sont la facilité de sa mise en œuvre sur les deux plates-formes ASIC et FPGA, la grande flexibilité pour l’authentification des circuits intégrés ainsi que la génération de clés de chiffrement. La deuxième structure proposée “TERO PUF” est basée sur le principe de cellules temporairement oscillantes. Elle exploite la métastabilité oscillatoire d’éléments couplés en croix, et peut aussi être utilisée pour un générateur vrai d’aléas (TRNG). Plus précisément, la réponse du PUF profite de la métastabilité oscillatoire introduite par une bascule SR lorsque les deux entrées S et R sont connectées au même signal d’entrée. Les résultats expérimentaux montrent le niveau de performances élevé des deux structures de PUF proposées. Ensuite, afin de comparer équitablement la qualité des différentes PUF à retard, nous proposons une méthode de caractérisation spécifique. Elle est basée sur des mesures statistiques des éléments à retard. Le principal avantage de cette méthode vient de sa capacité à permettre au concepteur d’être sûr que la fonction PUF aura les performances attendues avant sa mise en œuvre et sa fabrication. Enfin, en se basant sur les propriétés de non clonabilité et de l’imprévisibilité des PUF, nous présentons de nouvelles techniques d’authentification et de génération de clés de chiffrement en utilisant la “loop PUF” proposée. Les résultats théoriques et expérimentaux montrent l’efficacité des techniques introduites en termes de complexité et de fiabilité / Physically Unclonable Functions, or PUFs, are innovative technologies devoted to solve some security and identification issues. Similarly to a human fingerprint, PUFs allows to identify uniquely electronic devices as they produce an instance-specific signature. Applications as authentication or key generation can take advantage of this embedded function. The main property that we try to obtain from a PUF is the generation of a unique response that varies randomly from one physical device to another without allowing its prediction. Another important property of these PUF is to always reproduce the same response for the same input challenge even in a changing environment. Moreover, the PUF system should be secure against attacks that could reveal its response. In this thesis, we are interested in silicon PUF which take advantage of inherent process variations during the manufacturing of CMOS integrated circuits. We present several PUF constructions, discuss their properties and the implementation techniques to use them in security applications. We first present two novel PUF structures. The first one, called “Loop PUF” is a delay based PUF which relies on the comparison of delay measurements of identical serial delay chains. The major contribution brought by the use of this structure is its implementation simplicity on both ASIC and FPGA platforms, and its flexibility as it can be used for reliable authentication or key generation. The second proposed structure is a ring-oscillator based PUF cells “TERO PUF”. It exploits the oscillatory metastability of cross-coupled elements, and can also be used as True Random Number Generator (TRNG). More precisely, the PUF response takes advantage from the introduced oscillatory metastability of an SR flip-flop when the S and R inputs are connected to the same input signal. Experimental results show the high performance of these two proposed PUF structures. Second, in order to fairly compare the quality of different delay based PUFs, we propose a specific characterization method. It is based on statistical measurements on basic delay elements. The main benefit of this method is that it allows the designer to be sure that the PUF will meet the expected performances before its implementation and fabrication. Finally, Based on the unclonability and unpredictability properties of the PUFs, we present new techniques to perform “loop PUF” authentication and cryptographic key generation. Theoretical and experimental results show the efficiency of the introduced techniques in terms of complexity and reliability

A computação reconfigurável está se fortalecendo cada vez mais devido ao grande avanço dos dispositivos reprogramáveis e ferramentas de projeto de hardware utilizadas atualmente. Isso possibilita que o desenvolvimento de hardware torne-se bem menos trabalhoso e complicado, facilitando assim a vida do desenvolvedor. A tecnologia utilizada atualmente em projetos de computação reconfigurável é denominada FPGA (Field Programmable Gate Array), que une algumas características tanto de software (flexibilidade), como de hardware (desempenho). Isso fornece um ambiente bastante propício para desenvolvimento de aplicações que precisam de um bom desempenho, sem que estas devam possuir uma configuração definitiva. O objetivo deste trabalho foi implementar um barramento eficiente para possibilitar a comunicação entre diferentes CORES de um robô reconfigurável, que podem estar dispersos em diferentes dispositivos FPGAs. Tal barramento seguirá o padrão AMBA (Advanced Microcontroller Bus Architecture), pertencente à ARM. Todo o desenvolvimento do core completo do AMBA foi realizado utilizando-se a linguagem VHDL (Very High Speed Integrated Circuit Hardware Description Language) e ferramentas EDAs (Electronic Design Automation) apropriadas. É importante notar que, embora o barramento tenha sido projetado para ser utilizado em um robô, o mesmo pode ser usado em qualquer sistema on-chip. / The reconfigurable computing is each time more fortified, what leads to a great advance of reprogrammable devices and hardware design tools. This has become hardware development less laborious and complicated, thus, facilitating the life of the designer. The technology currently used in projects of reconfigurable computing is called FPGA (Field Programmable Gate Array), which combines some characteristics of software (flexibility) and hardware (performance). This technology provides a propitious environment to the development of applications that need a good performance. Those that don’t need a definitive configuration. The purpose of this work was to implement an efficient bus to make possible the communication among different modules of a reconfigurable robot. This bus is based on a bus standard called AMBA (Advanced Microcontroller Bus Architecture), which belongs to ARM. All the development of full AMBA core was carried through using VHDL (Very High Speed Integrated Circuit the Hardware Description Language) language and appropriated EDA (Electronic Design Automation) tools. It is important to notice that, even so the bus have been projected to be used in a robot, it could be used in any system on-chip.

O aumento constante da demanda por sistemas computacionais cada vez mais eficientes tem motivado a busca por sistemas híbridos customizados compostos por GPP (General Purpose Processor), FPGAs (Field-Programmable Gate Array) e GPUs (Graphics Processing Units). Quando utilizados em conjunto possibilitam otimizar a relação entre desempenho e consumo de energia. Tais sistemas dependem de técnicas que façam o mapeamento mais adequado considerando o perfil do código fonte. Nesse sentido, este projeto propõe uma técnica para realizar o mapeamento entre GPP e FPGA. Para isso, utilizou-se como base uma abordagem de mineração de dados que avalia a similaridade entre código fonte. A técnica aqui desenvolvida obteve taxas de acertos de 65,67% para códigos sintetizados para FPGA com a ferramenta LegUP e 59,19% para Impulse C, considerando que para GPP o código foi compilado com o GCC (GNU Compiler Collection) utilizando o suporte a OpenMP. Os resultados demonstraram que esta abordagem pode ser empregada como um ponto de decisão inicial no processo de mapeamento em sistemas híbridos, somente analisando o perfil do código fonte sem que haja a necessidade de execução do mesmo para a tomada de decisão. / The steady increasing on demand for efficient computer systems has been motivated the search for customized hybrid systems composed by GPP (general purpose processors), FPGAs (Field- Programmable Gate Array) and GPUs (Graphics Processing Units). When they are used together allow to exploit their computing resources to optimize performance and power consumption. Such systems rely on techniques make the most appropriate mapping considering the profile of source code. Thus, this project proposes a technique to perform the mapping between GPP and FPGA. For this, it is applied a technique based on a data mining approach that evaluates the similarity between source code. The proposed method obtained hit rate 65.67% for codes synthesized in FPGA using LegUP tool and 59.19% for Impulse C tool, whereas for GPP, the source code was compiled on GCC (GNU Compiler Collection) using OpenMP. The results demonstrated that this approach can be used as an initial decision point on the mapping process in hybrid systems, only analyzing the profile of the source code without the need for implementing it for decision-making.

Atualmente, otimizar uma arquitetura ou um sistema de software não significa, necessariamente, aumentar o seu desempenho computacional. Devido a popularização de sistemas embutidos energizados por bateria, um item de grande importância a ser otimizado é o consumo de energia. De forma a obedecer às restrições de consumo, pesquisadores têm concentrado seus esforços na criação de ferramentas que possibilitam a modelagem, a otimização e a estimação do consumo de energia. Nos últimos anos, FPGAs têm apresentado um grande desenvolvimento nos quesitos densidade, velocidade e capacidade de armazenamento. Essas características tornaram possível a construção de sistemas complexos formados por um ou mais processadores soft-core. Esse tipo de processador permite uma personalização detalhada de suas características arquiteturais, possibilitando uma melhor adequação às restrições de tempo e espaço em um projeto. O objetivo deste trabalho é construir um estimador de potência para softwares que têm como alvo o processador soft-core Nios II da Altera, permitindo saber com antecedência quanta energia será consumida devido à execução de programas e aplicações de robótica móvel. O modelo implementado neste trabalho foi testado com vários benchmarks padronizados e os resultados obtidos provaram ser bastante adequados para estimar a energia consumida por um programa, obtendo erros de estimação máximos de 4,78% / Nowadays, optimization of hardware and software systems does not necessarily mean increasing their computational performance. Due to the popularization of battery-operated embedded systems, energy comsumption has become a very critical issue. Several tools have been created to model, optimize, and estimate energy consumption, allowing power constraints to be achieved. Lately, FPGAs have presented great advancements on density, speed and storage capacity. Such characteristics made possible the implementation of complex systems comprising one or more soft-core processors. This kind of processors allows detailed customization of its architectural features, enabling timinig, and area constraints of a design to be reached. The aim of this work is to build a power estimator to predict the energy comsumption of a software running on the Altera Nios II soft-core processor. The implemented estimation model presented on this dissertation has been tested with several standard benchmarks and the results obtained have proven to be suitable for estimating the energy consumption of a software with a maximum error of 4.78%

A maioria dos sistemas embarcados hoje desenvolvidos utilizam complexos sistemas eletrônicos integrados em um único chip, os Systems-on-a-Chip (SoC). A análise do comportamento de uma aplicação em execução, ou seja, o profiling nesses sistemas não é uma tarefa trivial em virtude da complexidade dos SoCs e pela restrição de ferramentas de profiling adequadas. Neste contexto, este trabalho apresenta o P2L, uma ferramenta de profiling que se baseia em métricas de nível de instrução e função para o processador LEON3. O P2L fornece estatísticas detalhadas de uso do processador, memórias e barramento de programas em execução sem uso de instrumentação. A ferramenta é composta por um componente em hardware e drivers e aplicativos em software. Os resultados mostram que o P2L fornece medidas com erro inferior a 1% e overhead desprezível quando comparado ao tempo de execução nativa do programa e ao do profiler GNU gprof. / Most embedded systems developed today use complex electronic systems integrated into a single chip, the Systems-on-a-Chip (SoC). The analysis of the behavior of a running application or profiling in these systems is not a trivial task due to the complexity of the SoC and the restriction of appropriate profiling tools. In this context, this work presents P2L - a profiling tool that is based on instruction and function level metrics for the LEON3 processor. P2L provides detailed usage statistics of the processor, memories, and bus of running programs without the use of instrumentation. The tool consists of a component in hardware, drivers and applications software. The results show that P2L provides measures with an error less than 1% and negligible overhead compared to native runtime program and the GNU profiler gprof.