Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

We develop a new fully-automated transistor sizing tool for FPGAs that features area, delay and wire load modeling enhancements over prior work to improve its accuracy in advanced process nodes. We then use this tool to investigate a number of FPGA circuit design related questions in a 22nm process. We find that building FPGAs out of transmission gates instead of the currently dominant pass-transistors, whose performance and reliability are degrading with technology scaling, yields FPGAs that are 15% larger but are 10-25% faster depending on the allowable level of "gate boosting''. We also show that transmission gate FPGAs with a separate power supply for their gate terminal enable a low-voltage FPGA with 50% less power and good delay. Finally, we show that, at a possible cost in routability, restricting the portion of a routing channel that can be accessed by a logic block input can improve delay by 17%.

Controle de processos é uma das muitas aplicações que aproveitam as vantagens do uso da teoria de conjuntos nebulosos. Nesse tipo de aplicação, o controlador é, geralmente, embutido no dispositivo controlado. Esta dissertação propõe uma arquitetura reconfigurável eficiente para controladores nebulosos embutidos. A arquitetura é parametrizável, de tal forma, que permite a configuração do controlador para que este possa ser usado na implementação de qualquer aplicação ou modelo nebuloso. Os parâmetros de configuração são: o número de variáveis de entrada (N); o número de variáveis de saída (M); o número de termos linguísticos (Q); e o número total de regras (P). A arquitetura proposta proporciona também a configuração das características que definem as regras e as funções de pertinência de cada variável de entrada e saída, permitindo a escalabilidade do projeto. A composição das premissas e consequentes das regras são configuráveis, de acordo com o controlador nebuloso objetivado. A arquitetura suporta funções de pertinência triangulares, mas pode ser estendida para aceitar outras formas, do tipo trapezoidal, sem grandes modificações. As características das funções de pertinência de cada termo linguístico, podem ser ajustadas de acordo com a definição do controlador nebuloso, permitindo o uso de triângulos. Virtualmente, não há limites máximos do número de regras ou de termos linguísticos empregados no modelo, bem como no número de variáveis de entrada e de saída. A macro-arquitetura do controlador proposto é composta por N blocos de fuzzificação, 1 bloco de inferência, M blocos de defuzzificação e N blocos referentes às características das funções de pertinência. Este último opera apenas durante a configuração do controlador. A função dos blocos de fuzzificação das variáveis de entrada é executada em paralelo, assim como, os cálculos realizados pelos blocos de defuzzificação das variáveis de saída. A paralelização das unidades de fuzzificação e defuzzificação permite acelerar o processo de obtenção da resposta final do controlador. Foram realizadas várias simulações para verificar o correto funcionamento do controlador, especificado em VHDL. Em um segundo momento, para avaliar o desempenho da arquitetura, o controlador foi sintetizado em FPGA e testado em seis aplicações para verificar sua reconfigurabilidade e escalabilidade. Os resultados obtidos foram comparados com os do MATLAB em cada aplicação implementada, para comprovar precisão do controlador. / Process control is one of the many applications that benefits from fuzzy control. In this kind of application, the controller is usually embedded in the controlled device. This dissertation proposes a reconfigurable architecture for efficient embedded fuzzy controllers. The architecture is customizable, as it allows the controller configuration to be used to implement any fuzzy model. The configuration parameters are: the number of input variables (N); the number of output variables (M); the number of linguistic terms (Q); and the total number of rules (P). The proposed architecture also enables the configuration of the characteristics that define the rules and membership functions of each input and output variable, allowing for an optimal scalability of the project. The composition of the antecedent and consequent of the rules are configurable, according to the fuzzy model that is being implemented. A priori, the architecture supports triangular membership functions, but it can be extended to accommodate other forms, such as trapezium, without major modifications. The characteristics of the lines, forming the membership functions of the linguistic terms, can be adjusted according to the definition of the fuzzy model, allowing the use of non-isosceles and isosceles triangles. Virtually, there are no limits on the number of rules or linguistic terms used in the model, as well as the number of input and output variables. The macro-architecture of the proposed controller is composed of N fuzzification blocks, 1 inference block, M defuzzification blocks and N blocks to handle the characteristics of the membership functions. This block operates only during the controller setup. The work done by the fuzzification blocks of the input variables is executed in parallel, as well as the computation performed by the defuzzification blocks of the output variables. The duplication of the fuzzification and defuzzification blocks accelerates the process of yielding the final response of the controller. Several simulations were performed to verify the correct operation of the controller, which is specified in VHDL. In a second stage, to evaluate the controller performance, the architecture was synthesized into a FPGA and tested with six applications to verify the reconfigurability and scalability of the design. The results obtained were compared with the ones obtained from MATLAB for each of the implemented applications, to demonstrate the accuracy of the controller.

De nombreux aspects de notre vie courante reposent sur l'échange de données grâce à des systèmes de communication électroniques. Des algorithmes de chiffrement puissants garantissent alors la sécurité, la confidentialité et l'authentification de ces échanges. Néanmoins, ces algorithmes sont implémentés dans des équipements qui peuvent être la cible d'attaques. Plusieurs attaques visant les circuits intégrés sont rapportées dans la littérature. Parmi celles-ci, les attaques laser ont été rapportées comme étant très efficace. Le principe consiste alors à illuminer le circuit au moyen d'un faisceau laser afin d'induire un comportement erroné et par analyse différentielle (DFA) afin de déduire des informations secrètes.L'objectif principal de cette thèse est de fournir des outils de CAO efficaces permettant de sécuriser les circuits en évaluant les contre-mesures proposées contre les attaques laser et cela très tôt dans le flot de conception.Cette thèse est effectuée dans le cadre d'une collaboration étroite entre deux laboratoires de Grenoble INP : le LCIS et le TIMA. Ce travail est également réalisé dans le cadre du projet ANR LIESSE impliquant plusieurs autres partenaires, dont notamment STMicroelectronics.Un modèle de faute au niveau RTL a été développé afin d’émuler des attaques laser. Ce modèle de faute a été utilisé pour évaluer différentes architectures cryptographiques sécurisées grâce à des campagnes d'injection de faute émulées sur FPGA.Ces campagnes d'injection ont été réalisées en collaboration avec le laboratoire TIMA et elles ont permis de comparer les résultats obtenus avec d'autres modèles de faute. De plus, l'approche a été validée en utilisant une description au niveau layout de plusieurs circuits. Cette validation a permis de quantifier l'efficacité du modèle de faute pour prévoir des fautes localisées. De plus, en collaboration avec le CMP (Centre de Microélectronique de Provence) des injections de faute laser expérimentales ont été réalisées sur des circuits intégrés récents de STMICROELECTRONICS et les résultats ont été utilisés pour valider le modèle de faute RTL.Finalement, ce modèle de faute RTL mène au développement d'une contremesure RTL contre les attaques laser. Cette contre-mesure a été mise en œuvre et évaluée par des campagnes de simulation de fautes avec le modèle de faute RTL et d'autres modèles de faute classiques. / Many aspects of our current life rely on the exchange of data through electronic media. Powerful encryption algorithms guarantee the security, privacy and authentication of these exchanges. Nevertheless, those algorithms are implemented in electronic devices that may be the target of attacks despite their proven robustness. Several means of attacking integrated circuits are reported in the literature (for instance analysis of the correlation between the processed data and power consumption). Among them, laser illumination of the device has been reported to be one important and effective mean to perform attacks. The principle is to illuminate the circuit by mean of a laser and then to induce an erroneous behavior.For instance, in so-called Differential Fault Analysis (DFA), an attacker can deduce the secret key used in the crypto-algorithms by comparing the faulty result and the correct one. Other types of attacks exist, also based on fault injection but not requiring a differential analysis; the safe error attacks or clocks attacks are such examples.The main goal of the PhD thesis was to provide efficient CAD tools to secure circuit designers in order to evaluate counter-measures against such laser attacks early in the design process. This thesis has been driven by two Grenoble INP laboratories: LCIS and TIMA. The work has been carried out in the frame of the collaborative ANR project LIESSE involving several other partners, including STMicroelectronics.A RT level model of laser effects has been developed, capable of emulating laser attacks. The fault model was used in order to evaluate several different secure cryptographic implementations through FPGA emulated fault injection campaigns. The injection campaigns were performed in collaboration with TIMA laboratory and they allowed to compare the results with other state of the art fault models. Furthermore, the approach was validated versus the layout of several circuits. The layout based validation allowed to quantify the effectiveness of the fault model to predict localized faults. Additionally, in collaboration with CMP (Centre Microélectronique de Provence) experimental laser fault injections has been performed on a state of the art STMicroelectronics IC and the results have been used for further validation of the fault model. Finally the validated fault model led to the development of an RTL (Register Transfer Level) countermeasure against laser attacks. The countermeasure was implemented and evaluated by fault injection campaigns according to the developed fault model, other state of the art fault models and versus layout information.

Architectures reconfigurables dynamiquement offrent théoriquement excellent compromis entre performance et flexibilité. Pratiquement, ces architectures sont basées sur un ou plusieurs processeurs et plusieurs cellules reconfigurables. Une cellule reconfigurable peut charger, exécuter et décharger des accélérateurs matériels. Cette propriété permet la virtualisation des tâches matérielles. Dans ce contexte, une application peut prendre avantage de la flexibilité du logiciel et la performance du matériel. Dans les architectures reconfigurables actuels, les tâches matérielles sont limitées à une coopérative multi-tâches , depuis le temps de reconfiguration et l'heure de contexte stockage sont coûteux . Bien que le temps de reconfiguration est dépendante de l’architecture, le temps requis pour stocker ou restaurer le contexte dépend fortement des applications s'exécutant sur des tâches matériels. La réduction de ce temps des changements de contexte est obligatoire d'offrir à la tâche matérielle d'un multi- tâches préemptif, tout comme les tâches de logiciels. Plusieurs méthodes existent pour effectuer les opérations contexte commutateur matériel dans un contexte cellulaire homogène : chaîne de relecture dédiée sur tissus reconfigurables, des points de contrôle, de numérisation de la chaîne sur le contexte réel. Mais, rien n'a été proposé dans un contexte de tissu hétérogène (par exemple une accélération matérielle nuage fournir sur différents types de carte FPGA) .L'objectif de cette thèse est de proposer de nouvelles méthodes et algorithmes pour permettre le matériel des changements de contexte, même entre des cibles matérielles hétérogènes. Au cours de la thèse, l'étudiant devra :- Réaliser une bibliographie sur les méthodes du matériel du groupe de préemption existants dans le contexte cellulaire homogène.- Proposer des algorithmes qui permettent une solution légère et générique changement de contexte pour les tâches matérielles .- Valider ces algorithmes par leur intégration dans un flux de production d' accélérateur matériel . Ainsi, le flux prolongée peut générer, en plus de la tâche matérielle d'une application, le support matériel dédié pour des changements de contexte.- Proposer une stratégie de génération (multi- cible supplémentaire, ...) adapté pour cibles hétérogènes. La stratégie doit préserver les points de synchronisation entre les objectifs- Prototype de preuve de concepts sur la stratégie sur un nuage de FPGA. / Dynamically reconfigurable architectures offer theoretically excellent trade-off between performance and flexibility. Practically, these architectures are based on one or several processors and several reconfigurable cells. A reconfigurable cell can load, execute and unload hardware accelerators. This property enables virtualization of hardware tasks. In this context, an application can take benefit from both software flexibility and hardware performance. In current reconfigurable architectures, hardware tasks are limited to cooperative multi-tasking, since reconfiguration time and context-storing time are expensive. While reconfiguration time is architecture-dependent, the time required to store or restore the context strongly depends on applications running on hardware tasks. Reducing this context-switch time is mandatory to offer to hardware task a preemptive multi-tasking, just like software tasks. Several methods exist to perform the hardware context-switch operations in an homogeneous cell context: dedicated readback chain on reconfigurable fabrics, checkpoints, scan-chain on live context. But, nothing has been proposed in an heterogeneous fabric context (e.g. a cloud providing hardware acceleration on various kind of FPGA board).The goal of this thesis is to propose new methodologies and algorithms to enable hardware context-switch even between heterogeneous hardware targets. During the thesis, the student will have to:- Realize a bibliography on the existing hardware task preemption methods in homogeneous cell context.- Propose algorithms that enable a lightweight and generic context switch solution for hardware tasks.- Validate these algorithms by their integration in a hardware accelerator generation flow. Thus, the extended flow can generate in addition of the hardware task of an application, the dedicated hardware support for context-switch.- Propose an generation strategy (incremental, multi-target,...) suitable for heterogeneous targets. The strategy has to preserve synchronization points between targets- Prototype proof-of-concepts on the strategy on an FPGA cloud.

La complexité croissante des systèmes numériques amène les architectures reconfigurable telles que les Field Programmable Gate Arrays (FPGA) à être très fortement demandés en raison de leur facilité de (re)programmabilité et de leurs faibles coûts non récurrents (NRE). La re-configurabilité est réalisée grâce à de nombreux point mémoires de configuration. Cette re-configurabilité se traduit par une extrême flexibilité des applications implémentées et dans le même temps par une perte en surface, en performances et en puissance par rapport à des circuits intégrés spécifiques (ASIC) pour la même fonctionnalité. Dans cette thèse, nous proposons la conception de FPGA avec différentes technologies 3D pour une meilleure efficacité. Nous intégrons les blocs à base de mémoire résistives pour réduire la longueur des fils de routage et pour élargir l'employabilité des FPGAs pour des applications non-volatiles de faible consommation. Parmi les nombreuses technologies existantes, nous nous concentrons sur les mémoires à base d'oxyde résistif (OxRRAM) et les mémoires à pont conducteur (CBRAM) en évaluant les propriétés uniques de ces technologies. Comme autre solution, nous avons conçu un nouveau FPGA avec une intégration monolithique 3D (3DMI) en utilisant des interconnexions haute densité. A partir de deux couches avec l'approche logique-sur-mémoire, nous examinons divers schémas de partitionnement avec l'augmentation du nombre de couches actives intégrées pour réduire la complexité de routage et augmenter la densité de la logique. Sur la base des résultats obtenus, nous démontrons que plusieurs niveaux 3DMI est une alternative solide pour l'avenir de mise à l'échelle de la technologie. / The ever increasing complexity of digital systems leads the reconfigurable architectures such as Field Programmable Gate Arrays (FPGA) to become highly demanded because of their in-field (re)programmability and low nonrecurring engineering (NRE) costs. Reconfigurability is achieved with high number of point configuration memories which results in extreme application flexibility and, at the same time, significant overheads in area, performance, and power compared to Application Specific Integrated Circuits (ASIC) for the same functionality. In this thesis, we propose to design FPGAs with several 3D technologies for efficient FPGA circuits. First, we integrate resistive memory based blocks to reduce the routing wirelength and widen FPGA employability for low-power applications with non-volatile property. Among many technologies, we focus on Oxide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) devices by assessing unique properties of these technologies in circuit design. As another solution, we design a new FPGA with 3D monolithic integration (3DMI) by utilizing high-density interconnects. Starting from two layers with logic-on-memory approach, we examine various partitioning schemes with increased number of integrated active layers to reduce the routing complexity and increase logic density. Based on the obtained results, we demonstrate that multi-tier 3DMI is a strong alternative for future scaling.

Este trabalho visa propor uma metodologia de análise da variabilidade do tempo de atraso de propagação no FPGA. Para alcançar esse objetivo são utilizados três circuitos diferentes: o circuito 1 mede a diferença de atrasos de dois circuitos, o circuito 2 identifica o atraso menor de dois circuitos e, por fim, o terceiro circuito que consiste do oscilador em anel. Cada circuito foi avaliado individualmente numa estrutura BIST, implementada nos FPGA XC3S200-FT256 e EP2C35F672C6. Os métodos utilizados para análise dos dados foram a média móvel, o plano de mínimos quadrados e o teste t-student. A metodologia permitiu mostrar a variabilidade within-die e suas componentes sistêmica e randômica. / This work aims to propose a methodology of analysis of variability of propagation-delay time in FPGA. To achieve this goal three different circuits are implemented: the circuit 1 measures the delay difference of two logic paths, the circuit 2 identifies smallest delay of two logic paths, and finally the third circuit consists of a ring oscillator. Each circuit has been assessed individually in a BIST structure, implemented in FPGAs XC3S200-FT256 and EP2C35F672C6. The methods used for data analysis were the moving average, least-squares plane and the t-student test. The methodology has allowed to evaluate the within-die variability and its systemic and random components.

O Sistema Brasileiro de Televisão Digital estabeleceu como padrão de codificação de áudio o algoritmo MPEG-4 Advanced Audio Coding, mais precisamente nos perfis Low Complexity, High Efficiency versão 1 e High Efficiency versão 2. O trabalho apresenta um estudo detalhado sobre o padrão, contendo desde alguns conceitos da psicoacústica como o mascaramento até a metodologia de decodificação do stream codificado, sempre voltado para o mercado do SBTVD. É proposta uma arquitetura em hardware para um decodificador compatível com o padrão MPEG-4 AAC LC. O decodificador é separado em dois grandes blocos mantendo em um deles o banco de filtros, considerado a parte mais custosa em termos de processamento. No bloco restante é realizada a decodificação do espectro, onde ocorre a decodificação dos códigos de Huffman, o segundo ponto crítico do algoritmo em termos de demandas computacionais. Por fim é descrita a implementação da arquitetura proposta em VHDL para prototipação em um FPGA da família Cyclone II da Altera. / MPEG-4 Advanced Audio Coding is the chosen algorithm for the Brazilian Digital Television System (SBTVD), supporting the Low Complexity, High Efficiency version 1 and High Efficiency version 2 profiles. A detailed study of the algorithm is presented, ranging from psychoacoustics concepts like masking to a review of the AAC bitstream decoding process, always keeping in mind the SBTVD. A digital hardware architecture is proposed, in which the algorithm is split in two separate blocks, one of them containing the Filter Bank, considered the most demanding task. The other block is responsible for decoding the coded spectrum, which contains the second most demanding task of the system: the Huffman decoding. In the final part of this work the conversion of the proposed architecture into VHDL modules meant to be prototyped with an Altera Cyclone II FPGA is described.

Os sistemas eletrônicos digitais estão sendo cada vez mais utilizados em aplicações de telecomunicações, processamento de voz, instrumentação, biomedicina e multimídia. A maioria dessas aplicações requer algum tipo de processamento de sinal, sendo que essa função normalmente é executada em grande parte por um bloco digital. Além disso, considerando-se os diversos tipos de circuitos existentes num sistema, tais como memórias RAM (Random Access Memory) e ROM (Read Only Memory), partes operativas e partes de controle complexas, é cada vez mais importante a preocupação com o teste desses sistemas complexos. O aumento da complexidade dos circuitos a serem testados exige também um aumento na complexidade dos circuitos testadores (teste externo), tornando estes últimos muito caros. Uma alternativa viável é integrar algumas ou todas as funções de teste no próprio chip a ser testado. Por outro lado, essa estratégia pode resultar em um custo proibitivo em termos de área em silício.É interessante observar, no entanto, que se os testes e a função de processamento de sinal não necessitarem ser executados em paralelo, então é possível utilizar uma única área reconfigurável para realizar essas funções de uma maneira sequencial. Logo, este trabalho propõe uma arquitetura reconfigurável otimizada para a implementação desses dois tipos de circuitos (processamento digital de sinais e teste). Com esta abordagem pretende-se ter ganhos de área em relação tanto a uma implementação dedicada (full-custom) quanto a uma implementação em dispositivos reconfiguráveis comerciais. Para validar essas idéias, a arquitetura proposta é descrita em uma linguagem de descrição de hardware, e são mapeados e simulados algoritmos de teste e de processamento de sinais nessa arquitetura. S˜ao feitas estimativas da área ocupada pelas três abordagens (dedicada, dispositivo reconfigurável comercial e nova arquitetura proposta), bem como uma análise comparativa entre as mesmas. Também são feitas estimativas de atraso e frequência máxima de operação. / Digital electronic systems have been increasingly used in a large spectrum of applications, such as communication, voice processing, instrumentation, biomedicine, and multimedia. Most of these applications require some kind of signal processing. Most of this task is usually performed by a digital block. Moreover, these complex systems are composed of different kinds of circuits, such as RAM (Random Access Memory) and ROM (Read Only Memory) memories, complex datapaths and control parts. This way, the test of such systems is ever more important. Likewise, the increasingly complexity of the circuits to be tested requires more complex testers (external test), making the latter more expensive. An approach to address this problem is to embbed the test functions onto the chip to be tested itself. Nevertheless, this approach may bring a prohibitive cost in terms of area on silicon. However, if the test and the signal processing functions are not required to run in parallel, then it is possible to use the same reconfigurable area to implement these functions one after another. Thus, this work proposes an optimized reconfigurable architecture to implement this kind of circuits (digital signal processing and test). This approach intends to decrease the occupied area in comparison to a dedicated and also to a comercial reconfigurable device implementation. To validate these ideas, the proposed architecture is described using a hardware description language and some test and digital signal processing applications are mapped and simulated on this architecture. In this work an estimative of the occupied area by the three approaches (dedicated, comercial reconfigurable device, and the new proposed architecture) as well as a comparison analysis between them are performed. Likewise, a delay estimate is performed and the maximum operation frequency is evaluated.