This thesis focuses on planar filters operating at the circuit board level. Planar filters have gained increasing attention due to their low losses, wide bandwidths, and compact size, which are essential for modern communication systems. The introduction provides background information on the motivation for the study, along with its goals and research questions. Theoretical discussions cover fundamental aspects of filters, including an exploration of substrate properties such as FR-4, various transmission line types like microstrip, Stripline, and Suspended stripline, and the mathematics behind lumped element and distributed element filters. Different filter characteristics are considered, and a literature review examines previous methods, techniques, and software tools used for filter design to inform the methodology of this work.    Based on the literature review, CST (Computer Simulation Technology) and AWR (Applied Wave Research) are selected as software tools for simulation and design facilitation. An interdigital and a combline bandpass filter are used as references for a broadband filter. The study demonstrates that broader bandwidth filters can be achieved using high-pass and low-pass filters. Results present S-parameter data for simulated filters compared with fabricated and measured filters.   Simulation results indicate that Suspended stripline exhibits a wider bandwidth characteristic compared to microstrip. The fabricated and measured filters generally exhibit good agreement with simulation results, except for one case discussed in detail in section 6.2.1. The literature review and discussion also address the limitations of the FR-4 substrate for high-frequency applications and suggest alternative substrate types for this study.

[pt] Este trabalho de Tese apresenta a pesquisa e desenvolvimento de conexões de ondas guiadas sobre substratos semicondutores (SiGe, GaAs). A integração de circuitos digitais através de guias S-SIWG (Semiconductor Substrate Integrated Waveguide) utilizando formato de modulação QAM é avaliada e destacada. Conexões internas aos chips e entre chips são associadas com o novo padrão Gigabit Ethernet 802.3ba operando na taxa de 100 Gbit/s estendendo-se a aplicações de 0,5 – 1,5 Terahertz. É também apresentada a pesquisa e o desenvolvimento de guias e dispositivos de microondas utilizando substratos de baixo custo e altas perdas (FR-4), substratos cerâmicos de alta constante dielétrica (Er igual a 80) e aplicações em subsistemas híbridos integrados. / [en] This work presents the research, design and development of guided waves connections in semiconductor substrates (SiGe, GaAs). The integration of digital systems using Semiconductor Wave Guides (S-SIWG) with QAM modulation formats are highlighted. Ultra-fast inter-chip and inner-chip connections are associated with the new Gigabit Ethernet IEEE 802.3ba standard at 100Gbit/s extended to (0.5-1.5) Terahertz domain. Additionally fiber glass substrates with high losses (Teflon/FR-4) and high dielectric ceramic substrates (Er equal 80) are also developed to be integrated with microwave devices, analog printed circuits boards and high Speed digital circuits and systems.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Eutectic (63% tin-37% lead) or near-eutectic (40% tin-60% lead) tin-lead solder is widely used for creating electrical interconnections between the printed wiring board (PWB) and the components mounted on the board surface. For components mounted directly on the PWB mounting pads, that is, surface mounted components, the tin-lead solder also constitutes the mechanical interconnection. Eutectic solder has a melting point of 183°C (361°F). It is important to realize that its homologous temperature, defined as the temperature in degrees Kelvin over its melting point temperature (T(m)), also in degrees Kelvin, is defined as T/T(m). At room temperature (25°C = 298K), eutectic solder's homologous temperature is 0.65. It is widely acknowledged that materials having a homologous temperature ≥ 0.5 are readily subject to creep, and the solder joints of printed wiring assemblies are routinely exposed to temperatures above room temperature. Hence, solder joints tend to be subject to both thermal fatigue and creep. This can lead to premature failures during service conditions. The geometry, that is, the lead configuration, of the joints can also affect failure. Various geometries are better suited to withstand failure than others. The purpose of this paper is to explore solder joint failures of dual in-line (DIP) integrated circuit components, leadless ceramic chip carriers (LCCCs), and gull wing and J-lead surface mount components mounted on PWBs.