Micro processors built specifically for digital signal processing are DSP processors. DSP is one of the core technologies in rapidly growing applications like communications and audio processing. The estimated growth of DSP processors in the last 6 years is over 40%. The variety of DSP capable processors for various applications also increased with the rising popularity of DSP processors. The design flow and architecture of such processors are not commonly available to students for learning. This report is a structured approach to design and implementation of an embedded DSP processor core for voice, audio and video codec. The report focuses on the design requirement specification, senior instruction set and assembly manual release, micro architecture design and implementation of the core. Details about the core verification are also included in this report. The instruction set of this processor supports running basic kernels of BDTI benchmarking.

This thesis describes an optimising compiler for translating from SMV to CLP(B). The optimisation is aimed at reducing the number of required variables in order to decrease the size of the resulting BDDs. Also a partitioning of the transition relation is performed. The compiler uses an internal representation of a FSM that is built up from the SMV description. A number of rewrite steps are performed on the problem description such as encoding to a Boolean domain and performing the optimisations. The variable reduction heuristic is based on finding sub-circuits that are suitable for reduction and a state space search is performed on those groups. An evaluation of the results shows that in some cases the compiler is able to greatly reduce the size of the resulting BDDs.

Heritage is a concept that has received abundant critical attention within the academy. This study seeks to extend this critique by demonstrating the value of long-term ethnographic research and analysis of heritage processes on the Main Islands of Yap State, Federated States of Micronesia (FSM). As the FSM staff cultural anthropologist for 23 months, the author utilizes interview and participant observation data collected during a total of over 2 years in the field to uncover and analyze the production of cultural heritage discourses on Yap’s Main Islands. With a central goal to understand locally produced views and values of stakeholders toward their heritage, including what exactly it is they wish to preserve and why, findings were analyzed to generate culturally informed strategies that local communities can consider in order to best meet their heritage interests. Local discourses on heritage being produced by Yapese Main Islander stakeholders in Yap demonstrate views and values toward preserving primarily intangible elements of their heritage within the sphere of Chambers’ (2006) private heritage construct. Attending to the processes that facilitate private heritage transmission should therefore be a central strategy in preservation efforts. Additionally, a political economy approach to investigating the production of local discourses on heritage emerges as a productive alternative to the critical discourse analysis (CDA) paradigm that largely discounts the locally contingent historic, economic, social and political structures that are daily mediated as stakeholders look to the past to confront their presents and futures.

Es wurden verschieden Kodierungsarten fuer FSMs untersucht, schwerpunktmaessig Gray Code und andere Arten der hazardfreien Kodierung. Ein spezieller Kodierungsalgorithmus zur hazardfreien Kodierung wurde entwickelt und in eine Entwurfsumgebung implementiert. Ein weitere Schwerpunkt der Arbeit sind Codegeneratoren, die eine Verhaltensbeschreibung der FSM in Verilog oder in VHDL erzeugen.

In modernen Fahrzeugen befindet sich eine Vielzahl von Steuergeräten, die verschiedenste Funktionen, wie z.B. das Antiblockiersystem (ABS) realisieren. Die Funktionalitäten von Steuergeräten werden heute mit unterschiedlichen Methoden beschrieben. Eine dieser Methoden sind Message Sequence Charts (MSCs). Aufgrund der Freiheitsgrade von MSCs gibt es verschiedene Möglichkeiten gleiche Funktionalität unterschiedlich zu beschreiben. In dieser Arbeit wird eine Methode definiert, wie verschiedene MSCs hinsichtlich Funktionskompatibilität auf Basis von endlichen Automaten untersucht werden können. Diese Diplomarbeit ist in zwei Schwerpunkte gegliedert. Zum einen soll ein Konzept für die Transformation des MSCs in der entsprechenden Automaten-Darstellung und einen Vergleich-Algorithmus zur Rückwärtskompatibilitätsanalyse der endlichen Automaten entwickelt werden. Zum anderen ist es Aufgabe, die Methode auf Basis von Java zu implementieren und in die Software-Plattform CAMP zu integrieren.

The development of an AJAX-based web application involves several challenges as the webpage is updated by using the AJAX calls without reloading the entire page as in any traditional webpage. This prevents one from going back to the previous view of the page as the browser does not reload the entire page; instead it only updates the page. My hypothesis is that if an AJAX-based application is designed by using the software architecture style called the Representational State Transfer (REST), then it is possible to overcome these challenges, which cannot be handled by using web-services. In order to investigate this, the Material Properties Repository, an AJAX-based application was redesigned by using REST. The results support my initial hypothesis. In this process of designing MPR using REST, a generalized software engineering process was created for designing an AJAX-based application RESTfully.

No description available.

This thesis focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers, which were introduced by Wang and Leduc. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. / This thesis focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers, which were introduced by Wang and Leduc. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We first introduce the sampled-data setting from Wang, and then define the sampled-data properties he identified, including the SD controllability property. We then introduce Wang's formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We then discuss Wang's modular and centralized translation method. We next introduced new modular results for the SD controllability point 3.1, SD controllability point 3.2, SD controllability point 4, activity loop free and S-singular prohibitable behaviour that allow one to verify the properties using only a portion of the system, instead of having to construct the entire system model. This should allow faster verification times as well as allow larger systems to be verified. We then introduce for the first time algorithms to verify Wang's CS Deterministic and non self-loop ALF properties. The remainder of the thesis focuses on developing algorithms and software to automatically convert a TDES first into an FSM, and then into a VERILOG module. VERILOG is a hardware description language which allows our FSM to be compiled and implemented on digital logic devices such as an FPGA. We then tested our method by modelling a simple door locking system as TDES, checking that the system satisfies the required sampled-data properties, and then translating the result into VERILOG. The above algorithms and methods have all been implemented as a part of the graphical DES research tool, DESpot. / Thesis / Master of Computer Science (MCS)

In the introduction there is described a history of the post office. There is also outlined a current state and a future intention of Czech Post (Česká pošta s. p.). Further there is explained an issue of the formatting of the address side of postcards and writing. In another part there is a job description of the sorting machine SIEMENS IRV 3000 and also information on the location of this sorting machine at each collecting transport nodes. In the conclusion there is described a consideration to increase a number of appropriate mail pieces for the sorting machine.

Made available in DSpace on 2016-06-02T19:06:00Z (GMT). No. of bitstreams: 1 4747.pdf: 5016839 bytes, checksum: ca7594d5895754f4ee9eb215e548c3cc (MD5) Previous issue date: 2012-11-23 / Financiadora de Estudos e Projetos / In recent years, performance improvements in sequential microprocessors have been limited by physical and technological factors. For this reason, alternative approaches for high performance execution have gained importance. One of them is based in the use of reconfigurable hardware, implemented using FPGAs. However, conventional methods for programming those devices are notoriously complex, usually based on hardware description languages such as VHDL and Verilog. This work presents the development of a compilation framework to support the translation of a loop, described in C language, into its corresponding version for synthesis in reconfigurable hardware. The optimized execution is based on the loop pipelining technique, which requires advanced compiler support. That is achieved by using the Cetus compiler, enhanced by a number of modifications, and thus used as a basis for the semi-automatic generation of custom-hardware accelerators. In order to guide the compiler developments and validate its basic functionalities, two study cases were considered: one based on finite state machines as the method of choice for hardware modelling (EC-1), and another based on the LALP domain specific language. In both cases, the proposed compilation framework have shown to be a facilitator element for the development of high performance custom-hardware. / O aumento no desempenho de processadores sequenciais tem sido limitado severamente por fatores físicos e tecnológicos nos últimos anos. Dessa forma, abordagens alternativas para a execução com alto desempenho ganharam maior importância nos últimos anos. Uma delas baseia-se na utilização de hardware customizado, implementado utilizando-se FPGAs. Entretanto, os métodos convencionais para programação desses dispositivos são notoriamente complexos, normalmente baseados em linguagens como VHDL e Verilog. Este trabalho apresenta o desenvolvimento de um framework de compilação para auxiliar a transformação de um loop, escrito em linguagem C, em sua versão para hardware customizado. A execução otimizada baseia-se na técnica de loop pipelining, a qual exige suporte avançado de compilação. Este é conseguido utilizando o compilador Cetus, que após uma série de modificações, pode ser utilizado como base para a geração semi-automática de aceleradores em hardware customizado. Como forma de guiar o desenvolvimento do compilador e validar suas funcionalidades básicas, dois casos de estudo foram considerados: um baseado na utilização de máquinas de estados finitos como método para a modelagem de hardware (EC-1), e outro baseado na linguagem de domínio específico LALP (EC-2). Em ambos os casos, o framework de compilação proposto mostrou-se útil como elemento facilitador ao desenvolvimento de hardware customizado de alto desempenho.