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In this thesis, several design methodologies are presented to improve the reliability of dual traction inverters in hybrid electric vehicles (HEVs). Several power inverter topologies including the two-level voltage-source inverter, the boost voltage-source inverter, the Z-source inverter, and reduced-parts inverters are compared in terms of power ratings, volume, and efficiency. The comparison results show that the two-level voltage-source inverter presents higher efficiency, higher power density, and lower cost. Therefore, the back-to-back two-level voltage-source inverter is selected. DC-link capacitor and power modules are the most vulnerable components in dual traction inverters. The lifetime of capacitor is mainly determined by the core temperature. In this thesis, an interleaving control scheme is proposed to reduce the capacitor power loss by decreasing the total DC-link current harmonics. With reduced capacitor power loss, the core temperature of capacitor is reduced. Therefore, the lifetime of capacitor is improved. In addition, a fast electro-thermal model of traction inverters is proposed to estimate the junction temperatures of power devices. Practical switching losses are measured and thermal coupling effects between multiple devices are considered. The calculation rate of junction temperature is reduced by considering both power loss profiles and properties of the thermal impedance. With this model, over-temperature protection and lifetime evaluation can be implemented to enhance the reliability of traction inverters. Finally, a current sensor fault-tolerant operation scheme with six-phase current reconstruction technique is proposed to improve the reliability of dual inverters. In order to get the missing phase currents, the PWM signals are phase shifted to create the reconstruction conditions. With measured DC-link current, all phase-currents of dual inverters are obtained at the expense of slight degradation of maximum allowable modulation index. Therefore, when some or all of the phase current sensors are failed, the dual traction inverters can operate normally. / Thesis / Doctor of Philosophy (PhD)

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<p> In this thesis we develop a mathematical framework to express and reason about properties of fault-tolerant computing systems. The main idea behind this mathematical framework is to use axiomatic theories to specify systems. The standard logical operators allow us to describe the basic behavior of the system, while we use deontic predicates on actions to express prescriptions about the system's behavior. Deontic logics have proved to be useful for reasoning about legal and moral systems, where the situation is more or less similar to fault-tolerance: there exists a set of rules that states what the normal behaviours or scenarios are. Violations arise when these rules are not followed and, as a consequence, some actions must be performed to return to a normal or desirable state. We develop our own deontic logic, keeping in mind that we want to use it for specifying fault-tolerant systems. We investigate the properties of this logic, commenting on those that are relevant to the use of the logic in practice. We provide two different deductive systems; one of them is a standard (Hilbert style) deductive system, while the other one is a tableaux system, which can be applied automatically to prove properties of specifications.</p> <p> In any specification language, it is important to have at hand mechanisms which enable designers to modularize the system description; we investigate how to apply these mechanisms to the logics proposed in this thesis, and, in particular, we focus on how the modularization of specifications affects the local prescriptions of a module (or component). We study the problems that arise from the interaction between components. We show that, in some cases, we can guarantee that the locality of violations in a particular component is preserved. Some examples are provided throughout this thesis to illustrate how the ideas described below can be applied in practice. </p> / Thesis / Doctor of Philosophy (PhD)

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A large number of errors in digital systems are due to the presence of transient faults. This is especially true of microprocessor-based systems working in a radiation environment that experience transient faults due to single event upsets. These upsets cause a temporary change in the state of the system without any permanent damage. Because of their random and non-recurring nature, transient faults are difficult to detect and isolate, hence they become a source of major concern, especially in critical real-time application areas. Concurrent detection of these errors is necessary for real-time operation. Most existing fault tolerance schemes either use redundancy to mask effects of transient faults or monitor the system for abnormal operations and then perform recovery operation. Although very effective, redundancy schemes incur substantial overhead that makes them unsuitable for small systems. Most monitoring schemes, on the other hand, only detect control flow errors. A new approach called Concurrent Processor Monitoring for on-line detection of transient faults is proposed that attempts to achieve high error coverage with small error detection latency. The concept of the execution profile of an instruction is defined and is used for detecting control flow and execution errors. To implement this scheme, a watchdog processor is designed for monitoring operation of the main processor. The effectiveness of this technique is demonstrated through computer simulations. / Ph. D.