[No Abstract]

Thesis (M.Phil.)--City University of Hong Kong, 2006. / "Submitted to Department of Electronic Engineering in partial fulfillment of the requirements for the degree of Master of Philosophy" Includes bibliographical references (leaves 88-92)

Fault-tolerant vehicle design is an emerging inter-disciplinary research domain, which is of increasedimportance due to the electrification of automotive systems. The goal of fault-tolerant systems is to handleoccuring faults under operational condition and enable the driver to get to a safe stop. This paperpresents results from an extended survey on fault-tolerant vehicle design. It aims to provide a holisticview on the fault-tolerant aspects of a vehicular system. An overview of fault-tolerant systems in generaland their design premises is given as well as the specific aspects related to automotive applications. Thepaper highlights recent and prospective development of vehicle motion control with integrated chassiscontrol and passive and active fault-tolerant control. Also, fault detection and diagnosis methods arebriefly described. The shift on control level of vehicles will be accompanied by basic structural changeswithin the network architecture. Control architecture as well as communication protocols and topologiesare adapted to comply with the electrified automotive systems. Finally, the role of regulations andinternational standardization to enable fault-tolerant vehicle design is taken into consideration. / <p>Qc 20120730</p>

This thesis deals with the question of what resources are necessary and sufficient for quantum computational speedup. In particular, we study what resources are required to promote fault tolerant stabilizer computation to universal quantum computation. In this context we discover a remarkable connection between the possibility of quantum computational speedup and negativity in the discrete Wigner function, which is a particular distinguished quasi-probability representation for quantum theory. This connection allows us to establish a number of important results related to magic state computation, an important model for fault tolerant quantum computation using stabilizer operations supplemented by the ability to prepare noisy non-stabilizer ancilla states. In particular, we resolve in the negative the open problem of whether every non-stabilizer resource suffices to promote computation with stabilizer operations to universal quantum computation. Moreover, by casting magic state computation as resource theory we are able to quantify how useful ancilla resource states are for quantum computation, which allows us to give bounds on the required resources. In this context we discover that the sum of the negative entries of the discrete Wigner representation of a state is a measure of its usefulness for quantum computation. This gives a precise, quantitative meaning to the negativity of a quasi-probability representation, thereby resolving the 80 year debate as to whether this quantity is a meaningful indicator of quantum behaviour. We believe that the techniques we develop here will be widely applicable in quantum theory, particularly in the context of resource theories.

Embedded memories dominate area, power and cost of modern very large scale integrated circuits system on chips ( VLSI SoCs). Furthermore, due to process variations, it becomes challenging to design reliable energy efficient systems. Therefore, fault-tolerant designs will be area efficient, cost effective and have low power consumption. The idea of this project is to design embedded memories where reliability is intentionally compromised to increase storage density. Gain cell memories are smaller than SRAM and unlike DRAM they are logic compatible. In multilevel DRAM storage density is increased by storing two bits per cell without reducing feature size. This thesis targets multilevel read and write schemes that provide short access time, small area overhead and are highly reliable. First, timing analysis of reference design is performed for read and write operation. An analytical model of write bit line (WBL) is developed to have an estimate of write delay. Replica technique is designed to generate the delay and track variations of storage array. Design of replica technique is accomplished by designing replica column, read and write control circuits. A memory controller is designed to control the read and write operation in multilevel DRAM. A multilevel DRAM is with storage capacity of eight kilobits is designed in UMC 90 nm technology. Simulations are performed for testing and results are reported for energy and access time. Monte Carlo analysis is done for variation tolerance of replica technique. Finally, multilevel DRAM with replica technique is compared with reference design to check the improvement in access times.

A stator turn fault in a safety-critical drive application must be detected at its initial stage and imperatively requires an evasive action to prevent a serious accident caused by an abrupt interruption in the drive s operation. However, this is much challenging for the case of an interior permanent magnet synchronous motor (IPMSM) drives because of the presence of the permanent magnets that cannot be turned off at will. This work tackles the problem of increase the stator turn fault tolerance of IPMSM drives in safety-critical applications. This objective is achieved by an on-line turn fault detection method and a simple turn fault-tolerant operating strategy. In this work, it is shown that a stator turn fault in a current-controlled voltage source inverter-driven machine leads to a reduced fundamental positive sequence component of the voltage references as compared to the machine without a turn fault for a given torque reference and rotating speed. Based on this finding, a voltage reference-based turn fault detection method is proposed. In addition, it is also revealed that an adjustment to the level of the rotating magnetic flux in an appropriate manner can yield a significant reduction in the propagation speed of the fault and possibly prevention of the fault from spreading to the entire winding. This would be accomplished without any hardware modification. Based on this principle, a stator turn fault-tolerant operating strategy for IPMSM drives maintaining drive s availability is proposed. To evaluate these turn fault detection method and fault-tolerant operating strategy, an electrical model and a thermal model of an IPMSM with stator turn faults are derived. All the proposed models and methods are validated through simulations and experiments on a 10kW IPMSM drive.

Due to their programmable nature, Field Programmable Gate Arrays (FPGAs) offer a good test environment for reconfigurable systems. FPGAs can be reconfigured during the operation with changing demands. This feature, known as Runtime Reconfiguration (RTR), can be used to speed-up computations and reduce system cost. Moreover, it can be used in a wide range of applications such as adaptable hardware, fault tolerant architectures. This thesis is mostly concentrated on the runtime reconfigurable architectures. Critical properties of runtime reconfigurable architectures are examined. As a case study, a Triple Modular Redundant (TMR) system has been implemented on a runtime reconfigurable FPGA. The runtime reconfigurable structure increases the system reliability against faults. Especially, the weakness of SRAM based FPGAs against Single Event Upsets (SEUs) is eliminated by the designed system. Besides, the system can replace faulty elements with non-faulty elements during the operation. These features of the developed architecture provide extra safety to the system also prolong the life of the FPGA device without interrupting the whole system.

Growing complexity of Systems on Chip (SoC) introduces interconnection problems. As a solution for communication bottleneck the new paradigm, Networks on Chip (NoC), has been proposed. Along with high performance and reliability, NoC brings in area and energy constraints. In this thesis we mainly concentrate on keeping communication-centric design environment fault-tolerant while considering area overhead. The previous researches suggest the adoption solution for fault-tolerance from multiprocessor architectures. However, multiprocessor architectures have excessive reliance on buffering leading to costly solutions. We propose to reconsider general router model by introducing central buffers which reduces buffer size. Besides, we offer a new fault-tolerant routing algorithm which effectively utilizes buffers at hand without additional buffers out of detriment to performance.

In this thesis, we focus on the design of the fault-tolerant routing algorithm for the (n, k)-star graph. We apply the idea of collecting the limited global information used for routing on the n-star graph to the (n, k)-star graph. First, we build the probabilistic safety vector (PSV) with modified cycle patterns. Then, our routing algorithm decides the fault-free routing path with the help of PSV. In order to improve the routing performance with more faulty nodes, we dynamically assign the threshold for our routing algorithm. The performance is judged by the average length of routing paths. Compared with distance first search and safety level, we get the best performance in the simulations.

Thesis (Ph. D.)--University of Oregon, 2001. / Typescript. Includes vita and abstract. Includes bibliographical references (leaves 124-127). Also available for download via the World Wide Web; free to University of Oregon users.