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Variable Speed Limits Control for Freeway Work Zone with Sensor FaultsDu, Shuming January 2020 (has links)
Freeway work zones with lane closures can adversely affect mobility, safety, and sustainability. Capacity drop phenomena near work zone areas can further decrease work zone capacity and exacerbate traffic congestion. To mitigate the negative impacts caused by freeway work zones, many variable speed limits (VSL) control methods have been proposed to proactively regulate the traffic flow. However, a simple yet robust VSL controller that considers the nonlinearity induced by the associated capacity drop is still needed. Also, most existing studies of VSL control neglected the impacts of traffic sensor failures that commonly occur in transportation systems. Large deviations of traffic measurements caused by sensor faults can greatly affect the reliability of VSL controllers.
To address the aforementioned challenges, this research proposes a fault-tolerant VSL controller for a freeway work zone with consideration of sensor faults. A traffic flow model was developed to understand and describe the traffic dynamics near work zone areas. Then a VSL controller based on sliding mode control was designed to generate dynamic speed limits in real time using traffic measurements. To achieve VSL control fault tolerance, analytical redundancy was exploited to develop an observer-based method and an interacting multiple model with a pseudo-model set (IMMP) based method for permanent and recurrent sensor faults respectively. The proposed system was evaluated under realistic freeway work zone conditions using the traffic simulator SUMO.
This research contributes to the body of knowledge by developing fault-tolerant VSL control for freeway work zones with reliable performance under permanent and recurrent sensor faults. With reliable sensor fault diagnosis, the fault-tolerant VSL controller can consistently reduce travel time, safety risks, emissions, and fuel consumption. Therefore, with a growing number of work zones due to aging road infrastructure and increasing demand, the proposed system offers broader impacts through congestion mitigation and consistent improvements in mobility, safety, and sustainability near work zones. / Thesis / Doctor of Philosophy (PhD) / Freeway work zones can increase congestion with higher travel time, safety risk, emissions and fuel consumption. This research aims to improve traffic conditions near work zones using a variable speed limits control system. By exploiting redundant traffic information, a variable speed limit control system that is insensitive to traffic sensor failures is presented. The proposed system was evaluated under realistic freeway work zone conditions in a simulation environment. The results show that the proposed system can reliably detect sensor failures and consistently provide improvements in mobility, safety and sustainability despite the presence of traffic sensor failures.
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Fault-Tolerant Control of Autonomous Ground Vehicle under Actuator and Sensor FaultsJanakiraman, Vaishnavi January 2022 (has links)
No description available.
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Fault Estimation and Fault-tolerant Control for In-wheel Motor Electric VehiclesZhang, Guoguang January 2017 (has links)
No description available.
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FAULT DIAGNOSIS AND FAULT-TOLERANT CONTROL IN NONLINEAR SYSTEMSZHANG, XIAODONG 11 June 2002 (has links)
No description available.
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Fault Diagnosis and Fault-Tolerant Control of Quadrotor UAVsAvram, Remus C. 31 May 2016 (has links)
No description available.
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Active Fault Tolerant Model Predictive Control of a Turbofan Engine using C-MAPSS40kSaluru, Deepak Chaitanya 26 June 2012 (has links)
No description available.
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System level fault diagnosis by testable diagnosis arrayChu, Sung-Chi January 1987 (has links)
A computer system is defined to be a system of n functional components interconnected together in a prescribed fashion to perform a variety of functions. To ensure the correctness of system output, faults in the system must be detected, and faulty component(s) subsequently identified. To continue operation with degraded performance the system reconfigures with the remaining resources. This ideal fault tolerant capability hinges on the capability of the system to detect and locate fault(s). One method is to perform a fault diagnosis procedure periodically. In the PMC (Preparata, Metze, and Chien) model, each component has the capability to test and be tested at the system level by a combination of other components in the system. Based on this model, a number of fault diagnosis algorithms have been developed. These fault diagnosis algorithms are either complicated or have inherited the diagnostic hardcore problem or both. In this thesis, an innovative approach to system level fault diagnosis is taken.
A diagnosis device implemented by simple hardware is proposed that virtually eliminates the burden of complicated diagnosis algorithm and reduces the complexity of the diagnostic hardcore. This device is called a Testable Diagnosis Array, or TDA. It is constructed with very simple combinational logic cells. Its simplicity makes external testing easy. The diagnosis procedure is thus transferred to the logic of the cell and to the control structure of the TDA.
In this thesis, a TDA is defined based on the PMC model. A simple algorithm is developed to construct a TDA for any given system. The TDA is characterized, with respect to the testing assignments of a system. A class of t-TDA-diagnosable systems is defined. Necessary and sufficient conditions for t-TDA-diagnosable systems are derived. A number of special classes oft-diagnosable systems are shown to be t-TDA-diagnosable. Other results and topics for future research are discussed. / Ph. D.
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Parallel hardware accelerated switch level fault simulationRyan, Christopher A. 02 October 2007 (has links)
Switch level faults, as opposed to traditional gate level faults, can more accurately model physical faults found in an integrated circuit. However, existing fault simulation techniques have a worst-case computational complexity of O(n²), where n is the number of devices in the circuit. This paper presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. The parallel switch level fault simulation technique uses 9-valued logic, N and P-type switch state tables, and a minimum operation in order to simulate all faults in parallel for one switch. The circuit partitioning method uses reverse level ordering, grouping, and subgrouping in order to partition transistors for parallel processing. This paper also presents an algorithm and complexity measure for parallel fault simulation as extended to the switch level. For the algorithm, the switch level fault simulation complexity is reduced to O(L²), where L is the number of levels of switches encountered when traversing from the output to the input. The complexity of the proposed algorithm is much less than that for traditional fault simulation techniques. / Ph. D.
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Automated incorporation of upset detection mechanisms in distributed Ada systemsHeironimus, Elisa K. January 1988 (has links)
This thesis presents an automated approach to developing software that performs single event upset (SEU) detection in distributed Ada systems. Faults considered are those that fall in the single event upset (SEU) category. SEUs may cause information corruption leading to a change in program flow or causing a program to execute an infinite loop. Two techniques that detect the presence of these upsets are described. The implementation of these techniques is discussed in relation to the structure of Ada software systems and exploit the block structure of Ada.
A program has been written to automatically modify Ada application software systems to contain these upset detection mechanisms. The program, Software Modifier for Upset Detection (SMUD), requires little interactive information from a programmer and relies mainly on SMUD directives that are inserted into the application software prior to the modification process. A full description of this automated procedure is included.
The upset detection mechanisms have been incorporated into a distributed computer system model employing the MIL-STD-1553B communications protocol. Ada is used as the simulation environment to exercise and verify the protocol. The model used as a testbed for the upset detection mechanisms consists of two parts: the hardware model and the software implementation of the 1553B communications protocol. The hardware environment is described in detail, along with a discussion on the 1553B protocol. The detection techniques have been tested and verified at the high level using computer simulations. A testing methodology is also presented. / Master of Science
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High level strategy for detection of transient faults in computer systemsModi, Nimish Harsukh January 1988 (has links)
A major portion of digital system malfunctions are due to the presence of temporary faults which are either intermittent or transient. An intermittent fault manifests itself at regular intervals, while a transient fault causes a temporary change in the state of the system without damaging any of the components. Transient faults are difficult to detect and isolate and hence become a source of major concern, especially in critical real-time applications.
Since satellite systems are particularly susceptible to transient faults induced by the radiation environment, a satellite communications protocol model has been developed for experimental research purposes. The model implements the MlL-TD-1553B protocol, which dictates the modes of communication between several satellite systems. The model has been developed employing the structural and behavioral capabilities of the HILO simulation system.
SEUs are injected into the protocol model and the effects on the program flow are investigated. A two-tier detection scheme employing the concept of Signature Analysis is developed. Performance evaluation of the detection mechanisms is carried out and the results are presented. / Master of Science / incomplete_metadata
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