Thesis (Ph. D.)--Computing, Georgia Institute of Technology, 2008. / Committee Member: Ahamad, Mustaque; Committee Member: Eisenhauer, Greg; Committee Member: Milojicic, Dejan; Committee Member: Pu, Calton; Committee Member: Schwan, Karsten.

Thesis (Ph.D.) - Carleton University, 2006. / Includes bibliographical references (p. 248-260). Also available in electronic format on the Internet.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Electrical and Computer Engineering, 2007. / Includes bibliographical references.

Thesis (Ph. D.)--Ohio State University, 2005. / Title from first page of PDF file. Includes bibliographical references (p. 164-173).

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / ENGLISH ABSTRACT: The development of a control allocation system for use as part of a fault-tolerant control (FTC) system in unmanned aerial vehicles (UAVs) is presented. This system plays a vital role in minimising the possibility that a fault will necessitate the reconfiguration of the control, guidance or navigation systems of the aircraft by minimising the difference between the desired and achievable aircraft performance parameters. This is achieved by optimising the allocation of control effort commanded by the virtual actuators to the physical actuators present on the aircraft. A simple general six degree of freedom aircraft model is presented that contains all of the relevant terms needed to find the trim biases of the aircraft actuators and evaluate the performance of the virtual actuators. This model was used to develop a control allocation formulation that optimises the performance of the virtual actuators of the aircraft while minimising adverse effects and avoiding actuator saturation. The resulting problem formulation was formulated as a multi-objective optimisation problem which was solved using the sequential quadratic programming method. The control allocation system was practically implemented and tested. A number of failure categories of varying severity were defined and two aircraft with different levels of actuator redundancy were used to test the system. The control allocation algorithm was evaluated for each failure category, aircraft test case and for a number of differing control allocation system configurations. A number of enhancements were then made to the control allocation system which included adding frequency-based allocation and adapting the algorithm for an unconventional ducted-fan UAV. The control allocation system is shown to be applicable to a number of different conventional aircraft configurations with no alterations as well as being applicable to unconventional aircraft with minor alterations. The control allocation system is shown to be capable of handling both single and multiple actuator failures and the importance of actuator redundancy is highlighted as a factor that influences the effectiveness of control allocation. The control allocation system can be effectively used as part of a FTC system or as a tool that can be used to investigate control allocation and aircraft redundancy. / AFRIKAANSE OPSOMMING: Die ontwikkeling van ’n beheertoekenning sisteem vir gebruik as deel van ’n fout verdraagsame beheersisteem in onbemande lugvaartuie word voorgelê. Hierdie sisteem speel ’n essensiële rol in die vermindering van die moontlikheid dat ’n fout die herkonfigurasie van die beheer, bestuur of navigasiesisteme van die vaartuig tot gevolg sal hê, deur die verskil te verminder tussen die verlangde en bereikbare werkverrigtingsraamwerk van die vaartuig. Dit word bereik deur die optimisering van die toekenning van beheerpoging aangevoer deur die virtuele aktueerders na die fisiese aktueerders teenwoordig op die vaartuig. ’n Eenvoudige algemene ses grade van vryheid lugvaartuig model word voorgestel wat al die relevante terme bevat wat benodig word om die onewewigtigheid verstelling van die vaartuig se aktueerders te vind en die werksverrigting van die virtuele aktueerders te evalueer. Hierdie model is gebruik om ’n beheer toekenning formulering te ontwikkel wat die werkverrigting van die virtuele aktueerders van die vaartuig optimiseer terwyl nadelige gevolge verminder word asook aktueerder versadiging vermy word. Die gevolglike probleem formulering is omskryf as ’n multi-doel optimiserings probleem wat opgelos is deur gebruik van die sekwensiële kwadratiese programmerings metode. Die beheertoekenning sisteem is prakties geïmplementeer en getoets. ’n Aantal fout kategorieë van verskillende grade van erns is gedefinieer en twee vaartuie met verskillende vlakke van aktueerder oortolligheid is gebruik om die sisteem te toets. Die beheer toekenning algoritme is geëvalueer vir elke fout kategorie, vaartuig toetsgeval, asook vir ’n aantal verskillende beheertoekenning sisteem konfigurasies. ’n Aantal verbeterings is aangebring aan die beheertoekenning sisteem, naamlik die toevoeging van frekwensie gebaseerde toekenning en wysiging van die algoritme vir ’n onkonvensionele onbemande geleide waaier lugvaartuig. Die beheertoekenning sisteem is van toepassing op ’n aantal verskillende konvensionele vaartuig konfigurasies met geen verstellings asook van toepassing op onkonvensionele vaartuie met geringe verstellings. Die beheertoekenning sisteem kan beide enkel- en veelvoudige aktueerder tekortkominge hanteer en die belangrikheid van aktueerder oortolligheid is beklemtoon as ’n faktor wat die effektiwiteit van beheertoekenning beïnvloed. Die beheertoekenning sisteem kan effektief geïmplementeer word as deel van ’n fout verdraagsame beheersisteem of as ’n werktuig om beheertoekenning en vaartuig oortolligheid te ondersoek.

Thesis (MScEng)--Stellenbosch University, 2013. / ENGLISH ABSTRACT: In this thesis the strategy for performing System Identification on an aircraft is presented. The ultimate aim of this document is to outline the steps required for successful aircraft parameter estimation within a Fault Tolerant Control Framework. A brief derivation of the classical 6 degree-of-freedom aircraft model is firstly presented. The derivation gives insight into the aircraft dynamics that are to be used to estimate the aircraft parameters, and provides a basis for the methods provided in this thesis. Different techniques of System Identification were evaluated, resulting in the choice of the Regression method to be used. This method, based on the Least-Squares method, is chosen because of its simplicity of use and because it does not require as much computational time as the other methods presented. Regression methods, including a recursive algorithm, are then applied to aircraft parameter estimation and practical considerations such as Identifiability and corrupted measurements are highlighted. The determination of unknown measurements required for System Identification of aircraft parameters is then discussed. Methods for both estimating and measuring the Angle-of-Attack (AoA) and angular accelerations are presented. The design and calibration of an AoA probe for AoA measurements, as well as a novel method that uses distributed sensors to determine the angular accelerations is also presented. The techniques presented in this thesis are then tested on a non-linear aircraft model. Through simulation it was shown that for the given sensor setup, the methods do not provide sufficiently accurate parameter estimates. When using the Regression method, obtaining measurements of the angle-of-attack solely through estimation causes problems in the estimation of the aerodynamic lift coefficients. Flight tests were performed and the data was analyzed. Similar issues as experienced with estimation done on the non-linear aircraft simulation, was found. Recommendations with regards to how to conduct future flight tests for system identification is proposed and possible sources of errors are highlighted. / AFRIKAANSE OPSOMMING: In hierdie tesis word die strategie vir die uitvoering van Stelsel Identifikasie op 'n vliegtuig aangebied. Die uiteindelike doel van hierdie document is om die stappe wat nodig is vir 'n suksesvolle vliegtuig parameter beraming, binne 'n Fout Tolerante Beheer Raamwerk, uit eente sit. 'n Kort afleiding van die klassieke 6 graad-van-vryheid vliegtuig model word eerstens aangebied. Die afleiding gee insig in die vliegtuig dinamika wat gebruik moet word om die vliegtuig parameters te beraam, en bied 'n basis vir die metodes wat in hierdie tesis verskyn. Verskillende tegnieke van Stelsel Identifikasie is geëvalueer, wat lei tot gebruik van die regressie-metode. Hierdie metode is gekies as gevolg van sy eenvoudigheid en omdat dit nie soveel berekening tyd as die ander metodes vereis nie. Regressie metodes, insluitend 'n rekursiewe algoritme, word dan toegepas op vliegtuig parameter beraming en praktiese orwegings soos identifiseerbaarheid en korrupte metings word uitgelig. Die bepaling van onbekende afmetings wat benodig is, word vir Stelsel Identifisering van die vliegtuig parameters bespreek. Metodes om die invalshoek en hoekige versnellings te meet en beraam, word aangebied. Die ontwerp en kalibrasie van 'n invalshoek sensor vir invalshoek metings, sowel as 'n nuwe metode wat gebruik maak van verspreide sensore om die hoekversnellings te bepaal, word ook aangebied. Die tegnieke wat in hierdie tesis aangebied is, word dan op 'n nie-lineêre vliegtuig model getoets. Deur simulasie is dit getoon dat die metodes vir die gegewe sensor opstelling nie voldoende akkurate parameters beraam nie. Dit is ook bewys dat met die gebruik van die Regressie metode, die vekryging van metings van die invalshoek slegs deur skatting, probleme in die beraming van die aerodinamiese lug koëffisiente veroorsaak. Die tegnieke wat in hierdie tesis verskyn, word dan op werklike vlug data toegepas.Vlugtoetse is uitgevoer en die data is ontleed. Aanbeveling met betrekking tot hoe om toekomstige vlug toetse vir Stelsel Identifikasiete word voorgestel, en moontlike bronne van foute word uitgelig.

A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe duas soluções para lidar com este comportamento imprevisível das tecnologias futuras: a primeira solução, chamada MemProc, é uma arquitetura baseada em memória que propõe reduzir a taxa de falhas de aplicações embarcadas micro-controladas. Esta solução baseia-se no uso de memórias magnéticas, que são tolerantes a falhas induzidas por radiação, e área de circuito combinacional reduzida para melhorar a confiabilidade ao processar quaisquer aplicações. A segunda solução proposta aqui é uma implementação de um IP de infra-estrutura para o processador MIPS indicada para sistemas em chip confiáveis, devido a sua adaptação rápida e por permitir diferentes níveis de robustez para a aplicação. A segunda solução é também indicada para sistemas em que nem o hardware nem o software podem ser modificados. Os resultados dos experimentos mostram que ambas as soluções melhoram a confiabilidade do sistema que fazem parte com custos aceitáveis e até, no caso da MemProc, melhora o desempenho da aplicação. / Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes two solutions to cope with this unpredictable behavior of future technologies: the first solution, called MemProc, is a memory based architecture proposed to reduce the fault rate of embedded microcontrolled applications. This solution relies in the use magnetic memories, which are tolerant to radiation induced failures, and reduced combinational circuit area to improve the reliability when processing any application. The second solution proposed here is an infrastructure IP implementation for the MIPS architecture indicated for reliable systems-on-chip due to its fast adaptation and different levels of application hardening that are allowed. The second solution is also indicated for systems where neither the hardware nor the software can be modified. The experimental results show that both solutions improve the reliability of the system they take part with affordable overheads and even, as in the case of the MemProc solution, improving the performance results.

Dans les modules de puissance à connexion filaire de type wire-bonding (WB), les forts courants commutés (jusqu’à 200A pour une puce de 10x10mm²) imposent de faibles résistances et inductances d’interconnexion pour réduire la chute de tension et les surtensions. Pour cette raison, les concepteurs multiplient les fils de bonding de grand diamètre (jusqu’à 500μm) en parallèle. De plus, quand la surface de puce le permet, les WB sont soudés à au moins deux endroits différents pour améliorer la distribution du courant. A la différence d’un assemblage standard de type WB, dans un module de puissance de type Direct-Lead-Bonding (DLB), la puce et la diode sont généralement brasées d’un côté, via la technique du flip-chip, sur le dissipateur intégré. L’autre face est brasée ou frittée directement sur une broche (ou clip) interne large pour former la maille électrique grâce à une brasure à base d'étain, d’argent et de cuivre (SAC ou Sn-Ag-Cu), très épaisse pour éviter le claquage broche-terminaison de puce. Par conséquent, le DLB peut offrir une surface de contact plus performante sur les plans électrique et thermique que le WB, réduisant ainsi la résistance de contact d’environ 50% selon la bibliographie (d’un facteur dix selon nos simulations électromagnétiques), améliorant la distribution du courant dans les puces et homogénéisant la température au sein du composant. De plus, l’inductance parasite interne peut être atténuée de 57% comparé au WB selon la littérature. Si l’on aborde la dimension sécuritaire, la tenue en surintensité ou I²T d’un module de puissance WB rempli de gel de silicone est faible et procure un effet fusible naturel bien qu’imparfait (mode de défaut circuit-ouvert). Les fils de bonding subissent un phénomène de soulèvement même si leur design n’a pas été pensé dans ce sens. En remplaçant le gel par de la résine époxy, ce comportement se dégrade pour donner un mode de défaut intermédiaire dû à la limitation en température de la résine. A l’inverse, le DLB devrait montrer un très fort I²T et donc, un mode de défaut se rapprochant du court-circuit. Ces travaux proposent une approche innovante sur le thème du design des topologies de conversion sécurisées à tolérance de panne : pourquoi ne pas construire une topologie autour du mode de défaillance intrinsèque d’un module de puissance, au lieu de mettre en place des moyens classiques pour le contrecarrer, i.e. essayer d'isoler systématiquement le défaut avec des fusibles ? Le module de puissance DLB était le candidat idéal pour mettre à l’œuvre notre philosophie. Dans un premier temps, nous avons cherché à comparer les modes de défaillance des deux technologies, WB et DLB, grâce à des essais destructifs d’énergies maîtrisés. Les résistances de défaut, énergies critiques et I²T ont été mesurées sur un banc dédié, de même que des analyses d'endommagements des zones de défaillance ont été réalisées au sein du CNES-THALES Lab de Toulouse par une méthode non intrusive de type Lock-In-Thermography (LIT). Il a été montré que la technologie DLB pouvait présenter une résistance de défaut dix fois plus faible que celle de la technologie WB à même surface de puce et à même énergie de destruction. La présence du clip permet aussi de réduire le gradient thermique dans la région du défaut et de moins contraindre thermiquement l'encapsulant par rapport à la technologie WB. La forte épaisseur du joint de brasure broche – puce garantit aussi une meilleure métallisation par refusion de la zone de perçage et ainsi une résistance de défaut plus faible. Dans un second temps, les modules détruits WB et DLB ont subi des essais d’endurance sur 5 semaines, afin d’éprouver la robustesse et la stabilité de leur résistance de défaut à faible et fort courants. Les résultats montrent clairement la supériorité de la technologie DLB. Par la suite, une campagne de caractérisation thermique (Rth/Zth) des deux technologies WB et DLB a été réalisée sur la base d'un banc développé à cet effet. / In wire-bonding (WB) power-modules, high current commutated by fast power chips (up to 200A on a 10x10mm² chip) implies low resistance and low stray inductance interconnections in order to reduce voltage drop and overvoltage. For this purpose, designers use numerous large-diameter bonding wires (up to 500μm) in parallel. Whenever the die surface is large enough (like IGBTs), bonding wires are soldered at least in two different spots to improve current distribution. Compared to conventional WB structure, inside Direct-Lead-Bonding (DLB) power-modules, chip and diode are generally soldered on one side, using flip-chip method, to the heat spreader. The other side is directly soldered or sintered to the large inner lead (or clip) to form the electrical loop with a thick standard SAC soldering (Sn-Ag-Cu) in order to avoid electrical breakdown between chip and clip. Therefore, DLB would provide a wider bonding area than WB design, reducing the emitter contact resistance by almost 50% in the literature (by a factor of 10 according to our simulation results), improving current uniformity in the chips and thus resulting in a uniform surface temperature distribution inside the device. Besides, DLB internal inductance could be reduced to 57% of wire-bonded modules according to literature. Considering safety aspects, the overcurrent capability of a gel-filled wire-bonding power module is low and provides a natural but imperfect wire-fuse-effect (as an open-failure mode). Lift-offs happen even if WB design is not optimized for it. Replacing the gel with an epoxy resin, this behaviour gets worse and an intermediate failure-mode is reached due to the epoxy temperature limitation. On the opposite, DLB should have a very high overcurrent capability characteristic and thus short-failure mode behaviour. This work offers a quite new approach in the field of fault-tolerant structure design: what if we use the faulty power module in a new way, instead of getting rid of it using classic methods to disconnect it, i.e. systematically isolating the power device using fuses? The DLB power module was the perfect candidate to experience our philosophy. In the first place, a comparison of both technologies has been performed through post-fault-behaviour characterisation using controlled energy failure tests. Post-fault resistances, critical energies and overcurrent capability have been measured on a dedicated test-bench, along with defect localization and analysis through micro-section thanks to the CNES-THALES Lab in Toulouse, using non-intrusive Lock-In Thermography (LIT) method. Failed DLB power-modules have showed post-fault resistances 10 times lower than wire-bonded power-modules with the same die size and the same destruction energy. The clip also reduces temperature gradient around the defect location and thus, releases the resin’s thermal constraints compared to WB technology. The very thick solder joint between clip and chip ensures a better metallic reforming and therefore a less resistive post-fault resistance. In the second place, faulty power modules under low and high destruction energy, both WB and DLB, have been tested during 5 weeks for durability and robustness. Results clearly show DLB supremacy. Then, a long campaign of thermal characterization of both designs (Rth/Zth) has been carried out thanks to another dedicated bench. We have proposed a new heating technique setting the die in its linear mode, which avoids using a high current power supply. We have modelled both designs using COMSOL Multiphysics in order for them to be simulated and compared in terms of thermal resistance and impedance, electrical resistance and inductance. The DLB thermal diffuser effect has been analysed. Thermal resistances are very similar (~0,13°C/W) meanwhile, surprisingly, WB is better than DLB in terms of thermal impedance with a maximum difference of 20% at 0.1s.

A diminuição no tamanho dos transistores vem aumentando cada vez mais o número de funções que os dispositivos eletrônicos podem realizar. Apesar da diminuição do tamanho mínimo dos transistores, a velocidade máxima dos circuitos não consegue seguir a mesma taxa de aumento. Um dos grandes culpados apontados pelos pesquisadores são as interconexões entre os transistores e também entre os componentes. O aumento no número de interconexões dos circuitos traz consigo um significativo aumento do cosumo de energia, aumento do atraso de propagação dos sinais, além de um aumento da complexidade e custo do projeto dos circuitos integrados. Como uma possível solução a este problema é proposta a utilização de lógica multivalorada, mais especificamente, a lógica quaternária. Os dispositivos FPGAs são caracterizados principalmente pela grande flexibilidade que oferecem aos projetistas de sistemas digitais. Entretanto, com o avanço nas tecnologias de fabricação de circuitos integrados e diminuição das dimensões de fabricação, os problemas relacionados ao grande número de interconexões são uma preocupação para as próximas tecnologias de FPGAs. As tecnologias menores que 90nm possuem um grande aumento na taxa de erros dos circuitos, na lógica combinacional e sequencial. Apesar de algumas potenciais soluções começara a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe o uso de circuitos quaternários com modificações para tolerar falhas provenientes de eventos transientes. Como principal contribuição deste trabalho destaca-se o desenvolvimento de uma CLB (do inglês Configurable Logic Block) quaternária capaz de suportar eventos transientes e, na possibilidade de um erro, evitá-lo ou corrigi-lo. / The decrease in transistor size is increasing the number of functions that can be performed by the electronic devices. Despite this reduction in the transistors minimum size, the circuit’s speed does not follow the same rate. One of the major reasons pointed out by researchers are the interconnections between the transistors and between the components. The increase in the number of circuit interconnections brings a significant increase in energy consumption, propagation delay of signals, and an increase in the complexity and cost of new technologies IC designs. As a possible solution to this problem the use of multivalued logic is being proposed, more specifically, the quaternary logic. FPGA devices are characterized mainly by offering greater flexibility to designers of digital systems. However, with the advance in IC manufacturing technologies and the reduced size of the minimum fabricated dimensions, the problems related to the large number of interconnections are a concern for future technologies of FPGAs. The sub 90nm technologies have a large increase in the error rate of its functions for the combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes the use of quaternary circuits with modifications to tolerate faults from transient events. The main contribution of this work is the development of a quaternary CLB (Configurable Logic Block) able to withstand transient events and the occurrence of soft errors.

A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe duas soluções para lidar com este comportamento imprevisível das tecnologias futuras: a primeira solução, chamada MemProc, é uma arquitetura baseada em memória que propõe reduzir a taxa de falhas de aplicações embarcadas micro-controladas. Esta solução baseia-se no uso de memórias magnéticas, que são tolerantes a falhas induzidas por radiação, e área de circuito combinacional reduzida para melhorar a confiabilidade ao processar quaisquer aplicações. A segunda solução proposta aqui é uma implementação de um IP de infra-estrutura para o processador MIPS indicada para sistemas em chip confiáveis, devido a sua adaptação rápida e por permitir diferentes níveis de robustez para a aplicação. A segunda solução é também indicada para sistemas em que nem o hardware nem o software podem ser modificados. Os resultados dos experimentos mostram que ambas as soluções melhoram a confiabilidade do sistema que fazem parte com custos aceitáveis e até, no caso da MemProc, melhora o desempenho da aplicação. / Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes two solutions to cope with this unpredictable behavior of future technologies: the first solution, called MemProc, is a memory based architecture proposed to reduce the fault rate of embedded microcontrolled applications. This solution relies in the use magnetic memories, which are tolerant to radiation induced failures, and reduced combinational circuit area to improve the reliability when processing any application. The second solution proposed here is an infrastructure IP implementation for the MIPS architecture indicated for reliable systems-on-chip due to its fast adaptation and different levels of application hardening that are allowed. The second solution is also indicated for systems where neither the hardware nor the software can be modified. The experimental results show that both solutions improve the reliability of the system they take part with affordable overheads and even, as in the case of the MemProc solution, improving the performance results.