Essa dissertação propõe um algoritmo e um equipamento (hardware) para captação de imagens da pupila do olho humano e processamento das mesmas a fim de obter, de forma portátil, autônoma, segura, não invasiva e em tempo real, informações sobre a pupila. Mais especificamente, o objetivo é obter informações que permitam determinar o diâmetro da pupila, tanto de forma estática (pupila com tamanho estável, sem a incidência intencional de luz) quanto dinâmica (pupila variando devido à aplicação de luz com intensidade variável). Tal sistema pode ser utilizado no setor da saúde, por exemplo, para realização da pupilometria, exame feito na área de oftalmologia, ou para medição da velocidade de expansão da pupila, exame auxiliar no diagnóstico de uma série de doenças que afetam o sistema nervoso. / This dissertation proposes an algorithm and a corresponding hardware implementation capable of capturing images from the human eye and processing these images to obtain, in a portable, autonomous, secure, and non-invasive way, in real time, information regarding the pupil. More specifically, the objective is to obtain information that allows the equipment to determine the pupil's diameter, both in static form (i.e., with constant light intensity) and in dynamic form (pupil under varying light intensity). Such a system can be used in the health sector, for example, in exams such as pupillometry, a test done by ophthalmologists, or for measuring the pupil's expansion rate, a test used in the diagnosis of a series of diseases that affect the nervous system.

Essa dissertação propõe um algoritmo e um equipamento (hardware) para captação de imagens da pupila do olho humano e processamento das mesmas a fim de obter, de forma portátil, autônoma, segura, não invasiva e em tempo real, informações sobre a pupila. Mais especificamente, o objetivo é obter informações que permitam determinar o diâmetro da pupila, tanto de forma estática (pupila com tamanho estável, sem a incidência intencional de luz) quanto dinâmica (pupila variando devido à aplicação de luz com intensidade variável). Tal sistema pode ser utilizado no setor da saúde, por exemplo, para realização da pupilometria, exame feito na área de oftalmologia, ou para medição da velocidade de expansão da pupila, exame auxiliar no diagnóstico de uma série de doenças que afetam o sistema nervoso. / This dissertation proposes an algorithm and a corresponding hardware implementation capable of capturing images from the human eye and processing these images to obtain, in a portable, autonomous, secure, and non-invasive way, in real time, information regarding the pupil. More specifically, the objective is to obtain information that allows the equipment to determine the pupil's diameter, both in static form (i.e., with constant light intensity) and in dynamic form (pupil under varying light intensity). Such a system can be used in the health sector, for example, in exams such as pupillometry, a test done by ophthalmologists, or for measuring the pupil's expansion rate, a test used in the diagnosis of a series of diseases that affect the nervous system.

Le contexte incertain dans lequel évoluent les applications embarquées influencefortement ces dernières. L'objectif de disponibilité induit généralement une forteredondance matérielle et fonctionnelle. A l'inverse, le paramètre de consommation prôneun nombre et un fonctionnement à minima des ressources. Avec la réduction de latechnologie, la variabilité des procédés de fabrication induit la possibilité accrue dedéfaillances. De façon à garantir une qualité de service acceptable par l'utilisateur, et cesur la totalité de la durée de vie du circuit, il convient de mener des études associant dèsles phases amont les deux paramètres sûreté de fonctionnement et consommation. Cettethèse a pour objectif de proposer une nouvelle conception pour les réseaux de capteurssans fil, afin de réduire consommation d'énergie et d'augmenter la fiabilité du réseau. / The uncertain contexts in which recent WSN embedded applications evolve have bigimpact on these applications. Traditionally, the objective of availability generally doubleshardware and functional redundancy; it means that the overhead is doubled in term ofenergy and cost. Besides, wireless node system is powered by limited battery; hencepower consumption parameter is only set to a number of components and functionalitiesat minimum resources. However, due to the technology reduction, process variabilityconducts to increase the possibility of failures. In order to guarantee an acceptablequality of service for the users, and on the operating lifetime of the system, it should carrystudies at the upper phases involving both dependability and consumption constraints.This thesis aims to propose novel design for wireless sensor networks, in order to reduceenergy consumption and to increase network dependability.

This thesis presents a secure digital camera (SDC) that inserts biometric data into images found in forms of identification such as the newly proposed electronic passport. However, putting biometric data in passports makes the data vulnerable for theft, causing privacy related issues. An effective solution to combating unauthorized access such as skimming (obtaining data from the passport's owner who did not willingly submit the data) or eavesdropping (intercepting information as it moves from the chip to the reader) could be judicious use of watermarking and encryption at the source end of the biometric process in hardware like digital camera or scanners etc. To address such issues, a novel approach and its architecture in the framework of a digital camera, conceptualized as an SDC is presented. The SDC inserts biometric data into passport image with the aid of watermarking and encryption processes. The VLSI (very large scale integration) architecture of the functional units of the SDC such as watermarking and encryption unit is presented. The result of the hardware implementation of Rijndael advanced encryption standard (AES) and a discrete cosine transform (DCT) based visible and invisible watermarking algorithm is presented. The prototype chip can carry out simultaneous encryption and watermarking, which to our knowledge is the first of its kind. The encryption unit has a throughput of 500 Mbit/s and the visible and invisible watermarking unit has a max frequency of 96.31 MHz and 256 MHz respectively.

Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.

Indiana University-Purdue University Indianapolis (IUPUI) / In this thesis, 3D image segmentation is targeted to a Xilinx Field Programmable Gate Array (FPGA), and verified with extensive simulation. Segmentation is performed using the Expectation-Maximization with Maximization of the Posterior Marginals (EM/MPM) Bayesian algorithm. This algorithm segments the 3D image using neighboring pixels based on a Markov Random Field (MRF) model. This iterative algorithm is designed, synthesized and simulated for the Xilinx FPGA, and greater than 100 times speed improvement over standard desktop computer hardware is achieved. Three new techniques were the key to achieving this speed: Pipelined computational cores, sixteen parallel data paths and a novel memory interface for maximizing the external memory bandwidth. Seven MPM segmentation iterations are matched to the external memory bandwidth required of a single source file read, and a single segmented file write, plus a small amount of latency.

Multi-/many-core heterogeneous architectures are shaping current and upcoming generations of compute-centric platforms which are widely used starting from mobile and wearable devices to high-performance cloud computing servers. Heterogeneous many-core architectures sought to achieve an order of magnitude higher energy efficiency as well as computing performance scaling by replacing homogeneous and power-hungry general-purpose processors with multiple heterogeneous compute units supporting multiple core types and domain-specific accelerators. Drifting from homogeneous architectures to complex heterogeneous systems is heavily adopted by chip designers and the silicon industry for more than a decade. Recent silicon chips are based on a heterogeneous SoC which combines a scalable number of heterogeneous processing units from different types (e.g. CPU, GPU, custom accelerator). This shifting in computing paradigm is associated with several system-level design challenges related to the integration and communication between a highly scalable number of heterogeneous compute units as well as SoC peripherals and storage units. Moreover, the increasing design complexities make the production of heterogeneous SoC chips a monopoly for only big market players due to the increasing development and design costs. Accordingly, recent initiatives towards agile hardware development open-source tools and microarchitecture aim to democratize silicon chip production for academic and commercial usage. Agile hardware development aims to reduce development costs by providing an ecosystem for open-source hardware microarchitectures and hardware design processes. Therefore, heterogeneous many-core development and customization will be relatively less complex and less time-consuming than conventional design process methods. In order to provide a modular and agile many-core development approach, this dissertation proposes a development platform for heterogeneous and self-adaptive many-core architectures consisting of a scalable number of heterogeneous tiles that maintain design regularity features while supporting heterogeneity. The proposed platform hides the integration complexities by supporting modular tile architectures for general-purpose processing cores supporting multi-instruction set architectures (multi-ISAs) and custom hardware accelerators. By leveraging field-programmable-gate-arrays (FPGAs), the self-adaptive feature of the many-core platform can be achieved by using dynamic and partial reconfiguration (DPR) techniques. This dissertation realizes the proposed modular and adaptive heterogeneous many-core platform through three main contributions. The first contribution proposes and realizes a many-core architecture for heterogeneous ISAs. It provides a modular and reusable tilebased architecture for several heterogeneous ISAs based on open-source RISC-V ISA. The modular tile-based architecture features a configurable number of processing cores with different RISC-V ISAs and different memory hierarchies. To increase the level of heterogeneity to support the integration of custom hardware accelerators, a novel hybrid memory/accelerator tile architecture is developed and realized as the second contribution. The hybrid tile is a modular and reusable tile that can be configured at run-time to operate as a scratchpad shared memory between compute tiles or as an accelerator tile hosting a local hardware accelerator logic. The hybrid tile is designed and implemented to be seamlessly integrated into the proposed tile-based platform. The third contribution deals with the self-adaptation features by providing a reconfiguration management approach to internally control the DPR process through processing cores (RISC-V based). The internal reconfiguration process relies on a novel DPR controller targeting FPGA design flow for RISC-V-based SoC to change the types and functionalities of compute tiles at run-time.

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With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow. / Master of Science