Electromigration related damage in solder bumps is one of the emerging issues resulting from the fast scaling-down of features in semiconductor packages. Although the electromigration phenomenon has been intensively studied on silicon level interconnect lines since the late 1960s, it is far less understood in solder bumps. Electromigration in solder joints can be quite different from that of the interconnects due to the differences in material systems and structures. This study addressed the solder joint electromigration and contained three major objectives. The first objective of this study was to set up an effective experimental technique to examine the damage development and determine the time-to-failure in the electromigration tests. The structure and dimension of the flip chip solder bump is very different from that of the chip level interconnect. Consequently, the traditional failure tracking method based on 2-point resistance monitoring is no longer able to provide real-time damage evolution information. A test system based on a Wheat stone bridge circuit was introduced. The technique showed the capability of detecting milliohm resistance changes and could track the interfacial crack growth induced by electromigration damage. Other aspects of the experiment, such as temperature and current distribution inside the test structure, were also examined so that proper lifetime could be extrapolated from testing condition to normal working condition. The second objective was to examine the failure mechanisms in solder bump electromigration which could be significantly different between various solder bump systems. Pb-free and high-Pb solder alloys with different UBM configurations were studied. The research results showed that the most active region during solder bump electromigration was the under bump metallization (UBM) layer and its interface with the solder due to the intermetallic compound formation and UBM dissolution. Therefore, the electromigration-induced damage occurred mostly in this region. The failure mechanisms were found to be highly dependent on the material system as well as the temperature. The third objective was to determine the statistical lifetime of the flip chip solder bumps under electromigration. Lognormal distributions were used to fit the lifetime. The temperature and current dependence was assumed to follow Black's equation and the activation energies was calculated from that. The results showed that the traditional Black's equation might not be applicable to solder bump electromigration due to the different failure mechanism at different temperatures. Special attention is needed to set up design rules for maximum operating current and temperature for a solder bump structure when extrapolating data from high temperature. / text

A novel large-scale silicon system platform with 9.6cm² of active silicon interposer area is demonstrated. The platform contains three interposer tiles and two silicon bridges, and a novel self-alignment technology utilizing positive self-alignment structures (PSAS) and a novel mechanically flexible interconnect (MFI) technology are developed and used to align and interconnect tiles and bridges on an FR4 substrate. An accurate alignment < 8μm between silicon bridges and interposer tiles makes it possible to accommodate nanophotonics to enable a high bandwidth and low-energy system in the future. In addition, mechanically flexible interconnects and silicon bridges are used to provide electrical connections between interposer tiles without having to use motherboard-level interconnects. Finally, an elastomeric bump interposer is developed to enable the packaging of PSAS-enabled silicon systems, and PSAS' compatibility with a thermo-compression bonding process is demonstrated to enable a wide range of system configurations involving interposer tiles and bridges, including the multi-chip package configuration used with the elastomeric bump interposers.

Thesis (M.S.)--Auburn University, 2008. / Abstract. Vita. Includes bibliographical references (p. 134-144).

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Systems Science Dept., 2004 / Only abstract available. "At the request of the author, this graduate work is not available for purchase." Includes bibliographical references.

Additive manufacturing is revolutionizing the aerospace, transportation, energy, healthcare and various consumer product industries, replacing centralized manufacturing plants with more localized fabrication. 3D printing has become ubiquitous within these industries for prototyping and production. Currently, the smallest 3D printed features are on the order of a micron. While sufficient for some academic and industry applications, nanoscale features are required for the electronics industry and research endeavors. Optical lithography is still the workhorse for industrial nanofabrication utilizing large expensive commercial foundries. Here, an atomic scale 3D printer is presented with many of the features found in a complex semiconductor fabrication plant. This process is reproduced using three separate die with microelectromechanical systems (MEMS), which are bonded together to create an integrated 3D printer with the capability to print at the atomic scale. Due to the microscale size and surface areas of MEMS devices, they are extremely sensitive with rapid response times. These onboard MEMS devices replicate the functions of a thermal evaporator, patterning mask, mass sensor, heaters, temperature sensors and Van de Pauw setups. The assembled 3D printer dimensions are 3.8 mm x 2.5 mm x 1.8 mm (LxWxH) and it is therefore ideal for cryogenic environments. Quenched condensed thin film metals can be deposited using the atomic scale thermal evaporators in varying thicknesses up to approximately 50 nm. Replacing the atomic scale evaporators with microscale evaporators, the deposited film thickness can reach 3.5 microns. Evaporated films are monitored during and after the deposition with the embedded MEMS devices. While this particular 3D printing assembly is designed for research-scale investigations, the same technology could be extended to wafer-scale 3D printing with high resolution, rapid throughput, and reduced cost. / 2023-06-01T00:00:00Z

Environmental stress tests, or accelerated life tests, apply stresses to electronic packages that exceed the stress levels experienced in the field. In theory, these elevated stress levels are used to generate the same failure mechanisms that are seen in the field, only at an accelerated rate. The methods of assessing reliability of electronic packages can be classified into two categories: a statistical failure based approach and a physics of failure based approach. This research uses a statistical based methodology to identify the critical factors in reliability performance of a flip chip on board component level assembly and a physics of failure based approach to develop a low cycle strain based fatigue equation for flip chip component level assemblies. The critical factors in determining reliability performance were established via experimental investigation and their influence quantified via regression analysis. This methodology differs from other strain based fatigue approaches because it is not an empirical fit to experimental data; it utilizes regression analysis and least squares to obtain correction factors, or correction functions, and constants for a strain based fatigue equation, where the total inelastic strain is determined analytically. The end product is a general flip chip on board equation rather than one that is specific to a certain test vehicle or material set.

No description available.

No description available.

Avatrel 8000P's excellent photo-definition properties and mechanical strength make it an ideal polymer collar material. Avatrel 8000P is a high contrast, I-line sensitive mixture that can be developed in traditional aqueous-base developers. The great photolithographical performance of this photopolymer can be partly contributed to the minimal amount of light absorbed by the base norbornene polymer. The processing conditions noted in this work are an optimized version, which have been shown to give superior photolithographical performance. The simple baking procedures make Avatrel 8000P easier to process than SU-8. The ability to develop Avatrel 8000P in aqueous base can reduce chemical waste. As shown by SEM images, high fidelity structures with aspect ratios of 7:1 can be fabricated in thick films with vertical sidewalls. Bonding between two copper surfaces over various gap sizes was achieved by electroless deposition without the addition of surfactants or inhibitors in the bath. The effect of anneal temperature on the electroless bond formed was analyzed. The electroless bond strength increased with anneal temperature. However, the bond strength estimation for samples annealed at 80°C to 120°C is a minimum value due to the failure location of most of the pillars and the resulting area used in the calculation of bond strength. Grain growth from copper recrystallization and removal of small defects improve the bond strength. Large voids at the interface of the two pillars were related to rough starting surfaces for the electroplated pillars.