In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components. Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach. The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.

Body-channel communication (BCC) is based on the principle of electrical field data transmission attributable to capacitive coupling through the human body. It is gaining importance now a day in the scenario of human centric communication because it truly offers a natural means of interaction with the human body. Traditionally, near field communication (NFC) considers as a magnetic field coupling based on radio frequency identification (RFID) technology. The RFID technology also limits the definition of NFC and thus reduces the scope of a wide range of applications. In recent years BCC, after its first origin in 1995, regain importance with its valuable application in biomedical systems. Primarily, KAIST and Philips research groups demonstrate BCC in the context of biomedical remote patient health monitoring system. BCC transceiver mainly consists of two parts: one is digital baseband and the other is an analog front end (AFE). In this thesis, an analog front end receiver has presented to support the overall BCC. The receiver (Rx) architecture consists of cascaded preamplifier and Schmitt trigger. When the signals are coming from the human body, they are attenuated around 60 dB and gives weak signals in the range of mV. A high gain preamplifier stage needs to amplify these weak signals and make them as strong signals. The preamplifier single stage needs to cascade for the gain requirement. The single stage preamplifier, which is designed with ST65 nm technology, has an open loop gain of 24.01 dB and close loop gain of 19.43 dB. A flipped voltage follower (FVF) topology is used for designing this preamplifier to support the low supply voltage of 1 V because the topology supports low voltage, low noise and also low power consumption. The input-referred noise is 8.69 nV/sqrt(Hz) and the SNR at the input are 73.26 dB. The Schmitt trigger (comparator with hysteresis) is a bistable positive feedback circuit. It builds around two stage OTA with lead frequency compensation. The DC gain for this OTA is 26.94 dB with 1 V supply voltage. The corner analyzes and eye diagram as a performance matrix for the overall receiver are also included in this thesis work.

The complex and challenging process of construction supply chain management can involve tens of thousands of engineered components, systems, and subsystems, all of which must be designed in a multi-party and collaborative environment, the complexity of which is vastly increased in the case of megaprojects. A comprehensive Advanced Construction Supply Nexus Model (ACSNM) was developed as a computational and process-oriented environment to help project managers deal efficiently and effectively with supply chain issues: fragmentation, resource shortages, design delays, and planning and scheduling deficiencies, all of which result in decreased productivity, cost and time overruns, conflicts, and time-consuming legal disputes. To mitigate the effects of these difficulties, four new prototype systems are created: a front-end planning tool (FEPT), a construction value packaging system (CVPS), an integrated construction materials management (ICMM) system, and an ACSNM database. Because these components are closely interdependent elements of construction supply nexus management, the successfully developed model incorporates cross-functional integration. This research therefore effectively addresses process management, process integration, and document management, features not included in previous implementations of similar models for construction-related applications. This study also introduces new concepts and definitions, such as construction value packages comprised of value units that form the scope of value-added work defined by type, stage in the value chain, and other elements such as drawings and specifications. The application of the new technologies and methods reveals that the ACSNM has the potential to improve the performance and management of the enterprise-wide supply chain. Through opportunities provided by our industry partners, Coreworx Inc. and Aecon Group Inc., the elements of the developed model have been validated with respect to implementation using data from several construction megaprojects. The model is intended to govern current supply nexus processes associated with such megaprojects but may be general enough for eventual application in other construction sectors, such as multi-unit housing and infrastructure.

The business environment is changing rapidly, becoming very competitive and challenging for all firms, and particularly for small and medium enterprises (SMEs). As innovation and new product development represent valuable sources for SMEs’ future sustainability and development, making these processes more effective is essential. Previous literature, with the focus on large firms, underlined the importance of efficiently managing the early period of new product development (NPD), as this can reduce the product’s time to market and increase its performance. For this reason, contributing to a developed understanding of the challenges of medium-sized firms in managing this phase, the fuzzy front-end (FFE) of NPD, is the aim of this study. The theoretical framework of this study combines prior theories that relate to the difficulties, shortcomings, challenges that SMEs meet during the whole NPD process, including FFE, and theories that resulted from research on FFE in large firms. The structure is based on four elements referring to managing the idea generation process, new product development team, evaluation of product concept feasibility, and the organization of FFE. A qualitative strategy and a research design with two case studies on high-tech, medium-sized manufacturing firms were used in reaching the purpose of this study. This methodology choice reflects the explorative purpose of this research. The empirical data are mainly primary data, collected during three interviews with development managers and a product developer, completed as well with secondary data like general company information, collected from companies’ websites. The analysis of empirical findings revealed some relevant conclusions, which can bring value to the research area, and also to the practice. Our findings show that lack of communication with customers during the whole FFE phase, collecting limited or inaccurate information to be processed during this phase, finding the right formalization degree of FFE activities, determining the complexity of the product concept, and assessing external technology and expertise, represent the main challenges faced by medium-sized firms in the FFE of NPD. The study’s practical relevance consists in the advices and solutions suggested to managers for overcoming the challenges of the FFE phase and improving their results in the development projects. The theoretical implications reflect the importance of organizational size variable in association with the challenges of FFE. The sample of only two cases and the quality of the empirical data collected from two high-tech Swedish manufacturing firms which have a large focus on innovation are the main limitations of this study, as these medium-sized firms have gained some experience to face the specific challenges of FFE of NPD and the data they provide may be influenced by this aspect.

Modern communication systems require higher data rates which have increased thedemand for high speed transceivers. For a system to work efficiently, all blocks ofthat system should be fast. It can be seen that analog interfaces are the main bottleneckin whole system in terms of speed and power. This fact has led researchersto develop high speed analog to digital converters (ADCs) with low power consumption.Among all the ADCs, flash ADC is the best choice for faster data conversion becauseof its parallel structure. This thesis work describes the design of such a highspeed and low power flash ADC for analog front end (AFE) of a transceiver. Ahigh speed highly linear track and hold (TnH) circuit is needed in front of ADCwhich gives a stable signal at the input of ADC for accurate conversion. Twodifferent track and hold architectures are implemented, one is bootstrap TnH andother is switched source follower TnH. Simulations show that high speed with highlinearity can be achieved from bootstrap TnH circuit which is selected for the ADCdesign.Averaging technique is employed in the preamplifier array of ADC to reduce thestatic offsets of preamplifiers. The averaging technique can be made more efficientby using the smaller number of amplifiers. This can be done by using the interpolationtechnique which reduces the number of amplifiers at the input of ADC. Thereduced number of amplifiers is also advantageous for getting higher bandwidthsince the input capacitance at the first stage of preamplifier array is reduced.The flash ADC is designed and implemented in 150 nm CMOS technology for thesampling rate of 1.6 GSamples/sec. The bootstrap TnH consumes power of 27.95mW from a 1.8 V supply and achieves the signal to noise and distortion ratio(SNDR) of 37.38 dB for an input signal frequency of 195.3 MHz. The ADC withideal TnH and comparator consumes power of 78.2 mW and achieves 4.8 effectivenumber of bits (ENOB).

Body coupled communication (BCC) is a hot topic in personal networking domain. Many works arepublished suggesting different architectures for BCC since its inception in 1995 by Zimmerman. The number ofelectronic gadgets used by a single person increases as time pass by. Its a tedious job to transfer data betweenthen from a user point of view. Many of these gadgets can share their resources and save power and money.The existing wired or wireless networks does not meet the requirements for this network like scalable data rate,security etc. So here comes the novel idea of using human body as communication medium. The aim of thisthesis is to realize a hardware for BCC based on wide band signaling as part of a big project.The human body consists of 70% of water. This property makes the human body a fairly good conductor.By exploiting this basic property makes the BCC possible. A capacitance is formed if we place a metal platenear to the human body with the skin as a dielectric. This capacitance forms the interface between the humanbody and the analog front-end of the BCC transceiver. Any other metal structures near to the human body canattenuate the signal.A first-order communication link is established in software by the human body model and the transceiver inthe loop along with noise and interference. This communication link is used to verify the human body modeland the base band model done as part of the same big project. Based on the results a hardware prototype isimplemented. Measurements are taken in different scenarios using the hardware setup. The trade-off betweendesign parameters are discussed based on the results. At the end, it suggests a road map to take the projectfurther.

No description available.

Phased arrays eliminate the problems of mechanical steering by using fast and reliable electronic components for steering the main beam. Modeling and simulation of beam steering for 1D and 2D arrays is the aspect that is considered in this thesis. A 1D array with 4 elements and a 2D array with 16 elements are studied in the X-band (8-12 GHz). The RF front-end of a phased array radar is modeled by means of ADS Momentum (Advanced design system).

A study has been made in CMOS RF-switches that can be used in the front-end of a multi-band radio targeting the 802.11a,b,g and W-CDMA standards and working in the frequency range 2.4-5.5GHz. Especially, one single-transistor switch and two types of transmission gates have been analyzed, simulated and compared with respect to loss, linearity, compression point and noise. From this, five different single-transistor switches have been designed for on-chip probing measurements. Special consideration has been taken to accommodate on-chip testing, thus additional structures have been designed. The simulations and design has been performed with Chartered 0.18um RF-CMOS process. The results from the simulations show that the single-transistor switch has better performance in loss, linearity, compression point and noise compared to the transmission gates. However, for the transmission gates the linearity can be increased beyond the linearity of the single-transistor switch if the widths of the transistors are made sufficiently large. For the single-transistor switch, simulation results show that the transistor length shall be kept to its minimum for best performance and that the number of fingers does not influence significantly. Also, there are optimum values for the loss in on-mode, the noise and the linearity and worst-case values for the loss in off-mode when the transistor width is varied. Consequently, the single- transistor switch can be tuned by its transistor width to accommodate desired performances.

In this thesis, we analyze the performance of a loop-back built-in-self-test for a RF transceiver front-end. The tests aim at spot defects in a transceiver front-end and they make use of RF specifications such as NF (Noise Figure), G (power gain) and IIP3 (third order Intercept point). To enhance fault detectability, RF signal path sensitization is introduced. We use a functional RF transceiver model that is implemented in MatLab™ to verify this analysis.