Le travail présenté dans ce manuscrit a été effectué au sein de l’équipe de microélectronique de l’Institut de Recherche sur les lois Fondamentales de l’Univers (IRFU) du CEA. Il s’inscrit dans le contexte de la spectro-imagerie X et gamma pour la recherche en Astrophysique. Dans ce domaine, les futures expériences embarquées à bords de satellites nécessiteront des instruments d’imagerie à très hautes résolutions spatiales et énergétiques.La résolution spectrale d’une gamma-camera est dégradée par l’imperfection du détecteur lors de l’interaction photon-matière lui-même et par le bruit électronique. Si on ne peut réduire l’imprécision de conversion photon-charge du détecteur, on peut minimiser le bruit apporté par l’électronique de lecture. L’objectif de cette thèse est la conception d’une électronique intégrée de lecture de détecteur semi-conducteurs CdTe pixélisés pour gamma-caméra(s) compacte(s) et aboutable(s) sur 4 côtés à résolution spatiale « Fano limitée ». Les objectifs principaux de ce circuit intégré sont: un très bas bruit pour la mesure d’énergie des rayons-X, une très basse consommation, et une taille de canal de détection adaptée au pas des pixels CdTe. Pour concevoir une telle électronique, chaque paramètre contribuant au bruit doit être optimisé. L’hybridation entre l’électronique de lecture et le détecteur est également un paramètre clef qui fait généralement la résolution finale de l’instrument : en imposant une géométrie matricielle à l’ASIC adaptée au pas de 300 µm des pixels de CdTe, on peut espérer, réduire d’un facteur 10 la capacité parasite amenée par la connexion détecteur-électronique et améliorer d’autant le bruit électronique tout en conservant une densité de puissance constante. Une bonne connaissance des propriétés du détecteur nous permet alors d’extraire ses paramètres électroniques clefs pour concevoir l’architecture électronique de conversion et de filtrage optimale. Dans le cadre de cette thèse j’ai conçu deux circuits intégrés en technologies CMOS XFAB 0.18 µm. Le premier, Caterpylar, est destiné à caractériser cette nouvelle technologie, y compris en radiation, identifier un étage d’entrée pour le pixel adapté au détecteur, et valider par la mesure les résultats théoriques établis sur deux architectures de filtrage, semi gaussien et « Multi-Correlated Double Sampling » (MCDS), approchant l’efficacité du filtrage optimal et adaptées aux applications finales. Le deuxième circuit, D2R1, est un système complet, constitué de 256 canaux de lecture de détecteur CdTe, organisés dans une matrice de 16×16 pixels. Chaque canal comprend un préamplificateur de charge adapté à des pixels de 300 μm×300 μm, un opérateur de filtrage de type MCDS de profondeur programmable, d’un discriminateur auto-déclenché à bas seuil de détection programmable par canal. L’ASIC a été caractérisé sans détecteur et est en voie d’être hybridé à une matrice de CdTe très prochainement. Les résultats de caractérisations de la puce nue, en particulier en terme de produit puissance × bruit, sont excellents. La consommation de la puce est de 315 µW/ canal, la charge équivalente de bruit mesurée sur tous les canaux est de 29 électrons rms. Ces résultats valident le choix d’intégration d’un filtrage de type MCDS, qui est, à notre connaissance une première mondiale pour la lecture de détecteurs CdTe. Par ailleurs, ils nous permettent d’envisager d’excellentes résolutions spectrales de l’ensemble détecteur+ASIC, de l’ordre de 600 eV FWHM à 60 keV. / The work presented in this thesis is part of a project where a new instrument is developed: a camera for hard X-rays imaging spectroscopy. It is dedicated to fundamental research for observations in astrophysics, at wavelengths which can only be observed using space-borne instruments. In this domain the spectroscopic accuracy as well as the imaging details are of high importance. This work has been realized at CEA/IRFU (Institut de Recherche sur les lois Fondamentales de l’Univers), which has a long-standing and successful experience in instruments for high energy physics and space physics instrumentation. The objective of this thesis is the design of the readout electronics for a pixelated CdTe detector, suitable for a stacked assembly. The principal parameters of this integrated circuit are a very low noise for reaching a good accuracy in X-ray energy measurement, very low power consumption, a critical parameter in space-borne applications, and a small dead area for the full system combining the detector and the readout electronics. In this work I have studied the limits of these three parameters in order to optimize the circuit.In terms of the spectral resolution, two categories of noise had to be distinguished to determine the final performance. The first is the Fano noise limit. related to detector interaction statistics, which cannot be eliminated. The second is the electronic noise, also unavoidable; however it can be minimized through optimization of the detection chain. Within the detector, establishing a small pixel pitch of 300 μm reduces the input capacitance and the dark current. This limits the effects of the electronic noise. Also in order to limit the input capacitance the future camera is designed as a stacked assembly of the detector with the readout ASIC. This allows to reach extremely good input parameters seen by the readout electronics: a capacitance in range of 0.3 pF - 1 pF and a dark current below 5 pA.In the frame of this thesis I have designed two ASICs. The first one, Caterpylar, is a testchip, which enables the characterization of differently dimensioned CSA circuits to choose the most suitable one for the final application. It is optimized for readout of the target CdTe detector with 300 μm pixel pitch and the corresponding input parameters. With this circuit I have also analyzed possible filtering methods, in particular the semi-Gaussian shaping and the Multi-Correlated Double Sampling (MCDS). Their comparison is preceded by the theoretical analysis of these shapers. The second ASIC D2R1 is a complete readout circuit, containing 256 channels to readout CdTe detector with the same number of pixels, arranged in 16×16 array. Each channel fits into a layout area of 300 μm × 300 μm. It is based on the MCDS processing with self-triggering capabilities. The mean electronic noise measured over all channels is 29 electrons rms when characterized without the detector. The corresponding power consumption is 315 μW⁄channel. With these results the future measurements with the detector give prospects for reaching an FWHM spectral resolution in the order of 600 eV at 60 keV.

ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel. / ALICE é um dos quatro grandes experimentos do acelerador de partículas LHC (Large Hadron Collider) instalado no laboratório europeu CERN. Um programa de atualizações desse experimento acaba de ser aprovado pelo comitê gestor do acelerador LHC. Dentro das atualizações planejadas para os próximos anos do experimento ALICE, está melhorar a resolução e eficiência de rastreamento de partículas produzidas em colisões entre íons pesados, mantendo a excelente capacidade de identificação de partículas para uma taxa de leitura de eventos significativamente maior da atual. Para se alcançar esse objetivo, entre outras ações, é preciso atualizar os detectores Time Projection Chamber (TPC), modificando a eletrônica de leitura de eventos, a qual não é adequada para esta migração. Para superar esta limitação tem sido proposto o projeto, simulação, fabricação, teste experimental e validação de um ASIC protótipo de aquisição de sinais e de processamento digital chamado SAMPA, que possa ser usado na eletrônica de detecção dos sinais no cátodo do TPC, que suporte polaridades negativas de tensão de entrada e leitura continua de dados, com 32 canais por chip, com menor consumo de potência comparado com a versão anterior do chip. Este trabalho tem como objetivo o projeto, fabricação, e teste experimental de um readout front-end em tecnologia CMOS 130nm, com polaridade configurable (positiva/ negativa), peaking time e sensibilidade, de forma que o novo SAMPA ASIC possa ser usada em ambos detectores. Para obter um ASIC integrando 32 canais por chip, o projeto do front-end proposto precisa ter baixa área e baixo consumo de potência, mas ao mesmo tempo requer baixo ruido. Neste sentido, uma nova técnica para melhorar a especificação de ruido e o PSRR (Power Supply Rejection Ratio) sem impacto no consumo de área e potência é proposta neste trabalho. A análise e as equações do circuito proposto são apresentadas as quais foram validadas por simulação e teste experimental de um circuito integrado com 5 canais do front-end projetado. O Equivalent Noise Charge medido foi <550e para uma capacitance do detector de 18.5pF. A área total do front-end foi de 2300?m × 150?m, e o consumo total de potencia medido foi de 9.1mW por canal.

A critical issue that faces the Saudi Arabia Oil and Gas Sector (OGS)'s projects is the high level of uncertainty in the successful delivery of those projects. That high level of uncertainty makes it vital to monitor and control project performance for limiting financial losses, avoiding cost overruns, and improving predictability. One of the fundamental tools that sets the framework for project performance is the project Scope of Work (SOW). Having an effective project SOW at the front end the project is challenging for project practitioners and is an issue that needs to be addressed; as its development process and output can significantly affect the later stages of the project life cycle. The aim of this study was to develop a clearer understanding of the project SOW role in a project development and to make practical recommendations for its improvement by investigating project team members' perceptions of the SOW development process in two Saudi Arabian Oil and Gas companies. This research adopts a qualitative approach, a case study strategy and focus group discussions to collect primary data. The results suggested that the project SOW development process is the foundation for another twelve key project management processes that need to be considered in order to successfully complete a project On Scope, On Time, On Cost and On Strategy. To be considered effective, the project SOW should have the following four characteristics of: formality, usefulness, effective content elements and effective language quality. In addition, the project SOW should support effective decision making, risk management, project planning and project monitoring and control. The results show that the project SOW in Saudi Arabia OGS is developed in several phases as part of Front-End Loading (FEL) development and final project SOW is developed and approved at the end of the 2nd phase of FEL (FEL-2). It was found that there are eleven key enablers, such as clear vision, targets, and objectives; effective stakeholders' engagement; and effective assurance review process, for producing an effective project SOW. While eleven key barriers for producing an effective SOW were identified such as: absence of reward system; insufficient training programs; and insufficient budget. Therefore, enhancing the key enablers and overcoming the barriers may facilitated improvements in the project SOW development process. This study recommends that companies need to pay closer attention to the design of the temporary organisation and accordingly set their strategy, structure, process, rewards and people. The researcher details some implications, acknowledges some limitations and provides recommendations for future research in this area.

The Plasma Impedance Probe (PIP) is an electronic instrument that measures the impedance of a dipole antenna immersed in a plasma environment. Measurements made by the PIP provide valuable information regarding the plasma environment. Knowledge of ionospheric plasma density and density disturbances is required to understand radio frequency communication with satellites. The impedance curve provides us with significant plasma characteristics such as the electron-neutral collision frequency and plasma electron density. The work proposed here is a transistor-level implementation of the analog front-end, the non-inverting amplifier that is used to drive the antenna. The antenna immersed in plasma is excited with a sinusoidal/pulse stimulus and the output from the non-inverting configuration is fed into the difference amplifier. In the difference amplifier the output signal from the non- inverting amplifier is subtracted from the original stimulus and then fed into a high-speed pipeline data converter. The entire analog and mixed signal components are integrated on a single chip. The obvious advantages with this design are that it eliminates several sources of analog signal processing errors, thereby improving stability. A Fast Fourier Transform (FFT) is then applied on the sampled input stimulus as well as the processed signal. The input voltage FFT is then divided by the current FFT to obtain the antenna impedance. The FFT method helps in reducing transient errors and improves noise immunity of the system. The antenna impedance span curves over the frequency range from 100 kHz to 20MHz. The approach for the tranistor-level design is implementing short-channel design tech- niques using the gm/ID method. This is the primary focus of the thesis where the emphasis has been on using a simple and intuitive method to design the front-end amplifier in the TSMC .35 um technology. The design specifications for this amplifier are derived from the system-level simulations. The transition from a Printed Circuit Board (PCB)-based design to System on Chip (SOC) implementation is explored. This makes the design components highly specific to the application. The following are the design approaches used for the analog front-end design. * A detailed study of the various factors affecting the PIP instrument measurement capabilities from the previous works. * System-level simulation of the the entire PIP system to completely characterize the analog front-end. * Exploration of the possible design topologies for the transistor-level implementation. * A novel method of analog amplifier design using the gm/ID methodology. Miniaturization of the instrument and using a pulse-based measurement scheme also offer an immediate benefit to sounding rocket missions. The reduction of power, mass, and volume will enable the instrument to be flown on many more sounding rockets than at present. The faster measurement is especially valuable since the ionospheric plasma changes in character most rapidly with altitude.

本研究透過瞭解理論發展的過程, 辨識學術文獻在創新開端發展的樣式與軌跡, 並以之為基礎, 分析該學術領域之研究概況與趨勢. 分析之單元為理論建立之過程以及學術文獻; 本研究之文獻資料主要來自於Journal of Product Innovation Management, Management Science, Journal of Marketing, R&D Management, Technovation, IEEE Transactions on Engineering Management, Research Policy…等24份國際期刊, 共167篇文獻. 透過對於這些文獻的分析, 本研究辨識出三種類別, 14種研究的樣式與其相對應於理論建立過程的軌跡, 為理論建立過程提供了分類的依據, 同時也為”理論建立的理論(theory of theory-building)”提供了實徵研究的確認結果; 並以此樣式和軌跡為基礎, 分析創新開端目前研究的趨勢與概況, 提供創新開端領域目前學術研究概況的實徵數據; 本文最後將對本研究的限制提出說明, 以及對於未來可能的發展提出建議. / This study identifies trajectories and patterns of research towards theory-building in the early stage of front-end innovation. The trajectories and patterns serve as a tool to explore and analyze the trends and the landscape of current research situation in the domain of interest. The units of analysis are individual research project and the process of theory-building. The source of data come from 24 peer-review academic journals, including Journal of Product Innovation Management, Journal of Marketing, R&D Management, Technovation, Management Science, Research Policy…and so on. In total, 167 academic articles are collected for further analysis. The result demonstrates that 14 patterns and corresponding trajectories along the theory-building process are identified. This study also discusses the possibilities of a research pattern that could be followed by these patterns and trajectories. In the end of the study, specific contributions to the knowledge of the early stage of front-end innovation are listed and future research opportunities are also suggested.

La diminution des dimensions des transistors MOS, qui permet d'augmenter leur densité sur une puce, induit des effets parasites qui perturbent fortement le fonctionnement des dispositifs. Le silicium et son oxyde jusqu'alors utilisés pour le module de grille des transistors sont remis en question au profit de nouveaux matériaux : des métaux pour la grille, et des matériaux à forte permittivité diélectrique pour le diélectrique de grille.<br />Ce travail porte sur l'élaboration par gravure plasma d'une grille métallique polysilicium/TiN/HfO2 en vue d'une intégration pour les noeuds technologiques 45 nm et 32 nm. L'analyse des plasmas de gravure halogénés et des surfaces gravées par spectrométrie de masse, spectrométrie de photoélectrons X (XPS) et par des techniques de caractérisation morphologique (MEB, TEM, AFM) a permis de dégager les principaux mécanismes de gravure de TiN. Les stratégies de procédé de gravure de l'empilement de la grille et l'impact des procédés plasma sur l'intégrité des matériaux ont ensuite été discutés.<br />La gravure de TiN en plasma HBr est sélective vis à vis de la couche d'arrêt HfO2 mais elle génère de la pente dans les profils gravés, alors que le plasma de Cl2, plus réactif, conduit à une gravure latérale de la grille et induit des phénomènes de micro masquage. Cela impose un mélange HBr/Cl2 et une gravure à faible énergie de bombardement ionique pour la gravure sélective du métal.<br />La stratégie de gravure du silicium de la grille a du être repensée car l'intégration d'une couche métallique entre le silicium et le diélectrique de la grille modifie la distribution des charges statiques à<br />la surface de la couche d'arrêt, ce qui perturbe le contrôle dimensionnel des profils gravés. De plus la<br />gravure de TiN doit être anisotrope et sélective vis-à-vis de HfO2 tout en respectant l'intégrité de la partie supérieure de la grille en silicium. Ce travail montre que pour éviter la formation d'une encoche latérale à l'interface silicium/métal pendant la gravure du TiN il est nécessaire de contrôler à la fois les couches de passivation qui protègent les flancs du silicium et la composition chimique des dépôts qui recouvrent les parois du réacteur (car cette dernière influence les taux de recombinaison et donc les densités des atomes de Cl et de Br dans le plasma). Il est donc important de contrôler les étapes de conditionnement et de nettoyage des réacteurs de gravure.

<p>A study has been made in CMOS RF-switches that can be used in the front-end of a multi-band radio targeting the 802.11a,b,g and W-CDMA standards and working in the frequency range 2.4-5.5GHz. Especially, one single-transistor switch and two types of transmission gates have been analyzed, simulated and compared with respect to loss, linearity, compression point and noise. From this, five different single-transistor switches have been designed for on-chip probing measurements. Special consideration has been taken to accommodate on-chip testing, thus additional structures have been designed. The simulations and design has been performed with Chartered 0.18um RF-CMOS process. </p><p>The results from the simulations show that the single-transistor switch has better performance in loss, linearity, compression point and noise compared to the transmission gates. However, for the transmission gates the linearity can be increased beyond the linearity of the single-transistor switch if the widths of the transistors are made sufficiently large. </p><p>For the single-transistor switch, simulation results show that the transistor length shall be kept to its minimum for best performance and that the number of fingers does not influence significantly. Also, there are optimum values for the loss in on-mode, the noise and the linearity and worst-case values for the loss in off-mode when the transistor width is varied. Consequently, the single- transistor switch can be tuned by its transistor width to accommodate desired performances.</p>

<p>In this thesis, we analyze the performance of a loop-back built-in-self-test for a RF transceiver front-end. The tests aim at spot defects in a transceiver front-end and they make use of RF specifications such as NF (Noise Figure), G (power gain) and IIP3 (third order Intercept point). To enhance fault detectability, RF signal path sensitization is introduced. We use a functional RF transceiver model that is implemented in MatLab™ to verify this analysis.</p>

<p>In this master degree work, a digital attenuator and a low noise amplifier (LNA) have been designed and integrated with the RF front-end receiver for IEEE 802.11b Wireless LAN standard. Firstly, the 4-bit digitally controlled attenuator has been designed with theattenuation range of 50 to 80 dB and reflection coefficient less than -25 dB. Next, the single stage wide band low noise amplifier with voltage gain larger than 14 dB and noise figure below 4 dB has been designed to operate at frequency 2.4 GHz. Finally, the integration with a down-conversion mixer has been done and evaluated its performance.</p><p>The attenuator and low noise amplifier desired in this thesis have been implemented using standard CMOS 0.35µm technology and validated by the simulation tools Cadence Spectre-RF.</p>

<p>The business environment is changing rapidly, becoming very competitive and challenging for all firms, and particularly for small and medium enterprises (SMEs). As innovation and new product development represent valuable sources for SMEs’ future sustainability and development, making these processes more effective is essential. Previous literature, with the focus on large firms, underlined the importance of efficiently managing the early period of new product development (NPD), as this can reduce the product’s time to market and increase its performance. For this reason, contributing to a developed understanding of the challenges of medium-sized firms in managing this phase, the fuzzy front-end (FFE) of NPD, is the aim of this study.</p><p>The theoretical framework of this study combines prior theories that relate to the difficulties, shortcomings, challenges that SMEs meet during the whole NPD process, including FFE, and theories that resulted from research on FFE in large firms. The structure is based on four elements referring to managing the idea generation process, new product development team, evaluation of product concept feasibility, and the organization of FFE.</p><p>A qualitative strategy and a research design with two case studies on high-tech, medium-sized manufacturing firms were used in reaching the purpose of this study. This methodology choice reflects the explorative purpose of this research. The empirical data are mainly primary data, collected during three interviews with development managers and a product developer, completed as well with secondary data like general company information, collected from companies’ websites.</p><p>The analysis of empirical findings revealed some relevant conclusions, which can bring value to the research area, and also to the practice. Our findings show that lack of communication with customers during the whole FFE phase, collecting limited or inaccurate information to be processed during this phase, finding the right formalization degree of FFE activities, determining the complexity of the product concept, and assessing external technology and expertise, represent the main challenges faced by medium-sized firms in the FFE of NPD.</p><p>The study’s practical relevance consists in the advices and solutions suggested to managers for overcoming the challenges of the FFE phase and improving their results in the development projects. The theoretical implications reflect the importance of organizational size variable in association with the challenges of FFE.</p><p>The sample of only two cases and the quality of the empirical data collected from two high-tech Swedish manufacturing firms which have a large focus on innovation are the main limitations of this study, as these medium-sized firms have gained some experience to face the specific challenges of FFE of NPD and the data they provide may be influenced by this aspect.</p>