Hardware verification currently takes more than 50% of the whole verification time. There is a sustained effort to improve the efficiency of the verification process, which in the past helped deliver a large variety of supporting tools. The past years though did not see any major technology change that would bring the improvements that the process really needs (H. Foster 2013) (Wilson Research Group 2012). The existing approach to verification does not provide that type of qualitative jump anymore. This work is introducing a new tactic, providing a modern alternative to the existing approach to the verification problem. The novel approach I use in this research has the potential of significantly improve the process, way beyond incremental changes. It starts with acknowledging the huge amounts of data that follows the hardware development process from inception to the final product and in considering the data not as a quantitative by-product but as a qualitative supply of information on which we can develop a smarter verification. The approach is based on data already generated throughout the process currently used by verification engineers to zoom into the details of different verification aspects. By using existing machine learning approaches we can zoom out and use the same data to extract information, to gain knowledge that we can use to guide the verification process. This approach allows an apparent lack of accuracy introduced by data discovery, to achieve the overall goal. The latest advancements in machine learning and data mining offer a base of a new understanding and usage of the data that is being passed through the process. This work takes several practical problems for which the classical verification process reached a roadblock, and shows how the new approach can provide a jump in productivity and efficiency of the verification process. It focuses on four different aspects of verification to prove the power of this new approach: reducing effort redundancy, guiding verification to areas that need it first, decreasing time to diagnose, and designing tests for coverage efficiency. / text

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-08-15T15:44:40Z No. of bitstreams: 1 ANA KARINA DE OLIVEIRA ROCHA - DISSERTAÇÃO PPGCC 2008..pdf: 1111308 bytes, checksum: d22b0170a207a14988449565a953bfb2 (MD5) / Made available in DSpace on 2018-08-15T15:44:40Z (GMT). No. of bitstreams: 1 ANA KARINA DE OLIVEIRA ROCHA - DISSERTAÇÃO PPGCC 2008..pdf: 1111308 bytes, checksum: d22b0170a207a14988449565a953bfb2 (MD5) Previous issue date: 2008-05-16 / A necessidade de sistemas cada vez mais complexos é uma realidade em quase todas as áreas de aplicação da eletrônica. Os avanços recentes da microeletrônica possibilitam o surgimento de soluções inovadoras para diversos problemas do mundo moderno, devido à criação, em ritmo cada vez mais acelerado, de sistemas digitais de qualidade, sendo possível integrar dezenas de milhões de transistores em um único chip, com baixo custo operacional. Esses sistemas estão em constante evolução, impulsionada pelo desenvolvimento da indústria de semicondutores. Assim, há fortes pressões de mercado para a disponibilização de novos produtos com um número cada vez maior de funcionalidades. As implementações dos circuitos eletrônicos complexos necessitam da utilização de metodologias eficientes e automatizadas, que auxiliem na diminuição das falhas de projeto, a exemplo da metodologia de verificação funcional denominada VeriSC, que fornece testbenches e utiliza a biblioteca SCV (SystemC Verification Library), mas se restringe à verificação de circuitos digitais que processam transações temporais síncronas. O trabalho desenvolvido consiste na criação de um mecanismo de implementação de transações temporais, aplicada à metodologia de verificação funcional VeriSC, tornando-a uma metodologia de verificação eficiente também para circuitos digitais capazes de processar transações temporais assíncronas. / The necessity for more complex systems is a reality in almost all electronic application areas. Recent advances in microelectronics make possible the appearance of innovative solutions for several problems of the modern world, due to the creation in accelerated rhythm of quality digital systems, allowing the integration of tens of millions of transistors in a single chip with low operational cost. Those systems are in constant evolution promoted by the development of the semiconductors industry. Thus, there are strong pressures from the market to make new products available with an increasing number of functionalities. Implementations of complex electronic circuits must use of efficient and automated verification methodologies, which help in reducing design failures. In this context VeriSC, a functional verification methodology which provides testbenches and uses the SCV Library (SystemC Verification Library), but it is restricted to the digital circuit verification that has only synchronous time transactions. This work consists in creating a mechanism for the implementation of time transactions, applied to the VeriSC functional verification methodology, and in making it an efficient methodology for digital circuits capable of processing asynchronous time transactions.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-08-27T17:42:49Z No. of bitstreams: 1 HELDER FERNANDO DE ARAUJO OLIVEIRA - DISSERTAÇÃO PPGCC 2010..pdf: 2110687 bytes, checksum: 5d2a2c0f6c5039c3f21dd8219d20f122 (MD5) / Made available in DSpace on 2018-08-27T17:42:49Z (GMT). No. of bitstreams: 1 HELDER FERNANDO DE ARAUJO OLIVEIRA - DISSERTAÇÃO PPGCC 2010..pdf: 2110687 bytes, checksum: 5d2a2c0f6c5039c3f21dd8219d20f122 (MD5) Previous issue date: 2010-06-16 / O processo de desenvolvimento de um circuito digital complexo pode ser composto por diversas etapas. Uma delas é a verificação funcional. Esta etapa pode ser considerada uma das mais importantes, pois tem como objetivo demonstrar que as funcionalidades do circuito a ser produzido estão em conformidade com a sua especificação. Porém, além de ser uma fase com grande consumo de recursos, a complexidade da verificação funcional cresce diante da complexidade do hardware a ser verificado. Desta forma, o uso de uma metodologia de verificação funcional eficiente e de ferramentas que auxiliem o engenheiro de verificação funcional são de grande valia. Neste contexto, este trabalho realiza uma reformulação da metodologia de verificação funcional VeriSC, originando uma nova metodologia, denominada BVM (Brazil-IP Verification Methodology). VeriSC é implementada em SystemC e utiliza as bibliotecas SCV (SystemC Verification Library) e BVE (Brazil-IP Verification Extensions), enquanto BVM é implementada em SystemVerilog e baseada em conceitos e biblioteca de OVM (Open Verification Methodology). Além disto, este trabalho visa a adequação da ferramenta de apoio à verificação funcional eTBc (Easy Testbench Creator) para suportar BVM. A partir do trabalho realizado, é possível constatar, mediante estudos de caso no âmbito do projeto Brazil-IP, que BVM traz um aumento da produtividade do engenheiro de verificação na realização da verificação funcional, em comparação à VeriSC / The development process of a complex digital circuit can consist of several stages. One of them is the functional verification. This stage can be considered one of the most important because it aims to demonstrate that a circuit functionality to be produced is in accordance with its specification. However, besides being a stage with large consumption of resources, the complexity of functional verification grows according to the complexity of the hardware to be verified. Thus, the use of an effective functional verification methodology and tools to help engineer the functional verification are of great value. Within this context, this work proposes a reformulation of the functional verification methodology VeriSC, resulting in a new methodology called BVM (Brazil-IP Verification Methodology). VeriSC is implemented in SystemC and uses the SCV (SystemC Verification Library) and BVE (Brazil-IP Verification Extensions) libraries, while BVM is implemented and based on SystemVerilog and OVM (Open Verification Methodology) concepts and library. Furthermore, this study aims the adequacy of the functional verification tool eTBc (testbench Easy Creator), to support BVM. From this work it can be seen, based on case studies under the Brazil-IP project, that BVM increase the productivity of the engineer in the functional verification stage when compared to VeriSC.

This thesis focuses on the automation of scenarios creation for Portable Stimulus standard. The main goal of the work is an automatic generation of tests, which are defined as graphs for the Questa inFact tool from the Mentor company. For the automation I used an evolutionary algorithm with using a grammatical evolution.  The generated scenarios are connected to the existing verification environment based on UVM methodology, then the verification of the connected component is started. Based on the achieved functional and structural coverage, the individual's fitness value is calculated and propagated into an evolutionary algorithm.  At the end of the work, experiments are performed on the timer component and the contribution of the proposed evolutionary algorithm is evaluated. The proposed evolutionary algorithm is configurable by  grammar and user-defined basic transactions, which allows a wide range of uses. The evolutionary algorithm managed to achieve high functional and structural coverage on the verified timer component.

In the development process of digital circuits, it is often not possible to avoid introducing errors into systems that are being developed. Early detection of such errors saves money and time. This project deals with automation of feedback in functional verification of various data processing components. The goal of automatic feedback is not only to shorten the time needed to verify the functionality of a system, but mainly to improve verification coverage of corner cases and thus increase the confidence in the verified system. General functional and formal verification principles and practices are discussed, coverage metrics are presented, limitations of both techniques are mentioned and room for improvement of current status is identified. Design of feedback verification environment using a genetic algorithm is described in detial. The verification results are summarized and evaluated.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-11-07T17:16:29Z No. of bitstreams: 1 GEORGE SOBRAL SILVEIRA - TESE PPGEE 2012..pdf: 4756019 bytes, checksum: 743307d8794218c3a447296994c05332 (MD5) / Made available in DSpace on 2018-11-07T17:16:29Z (GMT). No. of bitstreams: 1 GEORGE SOBRAL SILVEIRA - TESE PPGEE 2012..pdf: 4756019 bytes, checksum: 743307d8794218c3a447296994c05332 (MD5) Previous issue date: 2012-08-10 / Capes / A indústria de semicondutores tem investido fortemente no desenvolvimento de sistemas complexos em um único chip, conhecidos como SoC (System-on-Chip). Com os diversos recursos adicionados ao SoC, ocorreu o aumento da complexidade no fluxo de desenvolvimento, principalmente no processo de verificação e um aumento do seu consumo energético. Entretanto, nos últimos anos, aumentou a preocupação com a energia consumida por dispositivos eletrônicos. Dentre as diversas técnicas utilizadas para reduzir o consumo de energia, Power Gating tem se destacado pela sua eficiência. Ultimamente, o processo de verificação dessa técnica vem sendo executado no nível de abstração RTL (Register TransferLevel), com base nas tecnologias CPF (Common Power Format) e UPF (Unified Power Format). De acordo com a literatura, as tecnologias que oferecem suporte a CPF e UPF, e baseadas em simulações, limitam a verificação até o nível de abstração RTL. Nesse nível, a técnica de Power Gating proporciona um considerável aumento na complexidade do processo de verificação dos atuais SoC. Diante desse cenário, o objetivo deste trabalho consiste em uma abordagem metodológica para a verificação funcional no nível ESL (Electronic System-Level) e RTL de circuitos digitais que empregam a técnica de Power Gating, utilizando uma versão modificada do simulador OSCI (Open SystemC Initiative). Foram realizados quatro estudos de caso e os resultados demonstraram a eficácia da solução proposta. / The semiconductor industry has strongly invested in the development of complex systems on a single chip, known as System-on-Chip (SoC), which are extensively used in portable devices. With the many features added to SoC, there has been an increase of complexity in the development flow, especially in the verification process, and an increase in SoC power consumption. However, in recent years, the concern about power consumption of electronic devices, has increased. Among the different techniques to reduce power consumption, Power Gating has been highlighted for its efficiency. Lately, the verification process of this technique has been executed in Register Transfer-Level (RTL) abstraction, based on Common Power Format (CPF) and Unified Power Format (UPF) . The simulators which support CPF and UPF limit the verification to RTL level or below. At this level, Power Gating accounts for a considerable increase in complexity of the SoC verification process. Given this scenario, the objective of this work consists of an approach to perform the functional verification of digital circuits containing the Power Gating technique at the Electronic System Level (ESL) and at the Register Transfer Level (RTL), using a modified Open SystemC Initiative (OSCI) simulator. Four case studies were performed and the results demonstrated the effectiveness of the proposed solution.

Made available in DSpace on 2015-05-14T12:36:33Z (GMT). No. of bitstreams: 1 Arquivototal.pdf: 3633724 bytes, checksum: f53669bf4f692585666fd625941bdbe0 (MD5) Previous issue date: 2012-07-31 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / The amount of data generated and transmitted by satellites to ground stations is always growing. As the technology advances, space imaging systems, especially those present in Earth observing missions, use equipment of increasing resolutions. Hence, it is necessary to ensure that this great quantity of data arrives at their destination reliably. Among some techniques involved, data compression plays an important role to accomplish this requirement. A data compression system for this purpose must comply with some conditions, particularly regarding performance. In this context, hardware implementations based on prediction and Golomb-Rice coding has achieved excellent results considering hardware and compression performance in both lossless and lossy cases. This work proposes a digital hardware approach of a low complexity satellite image lossless compressor based on prediction and Golomb-Rice coding that is attuned to the balance between performance requirements and error propagation, a common issue in space systems environment that is enhanced by data compression. In order to validate and analyze the compressor, a functional verification and FPGA prototyping methodology were followed. Given an image set from Brazilian's National Institute for Space Research (INPE, in the Portuguese acronym), CBERS-2B satellite, its results in FPGA show that this compressor achieves average compression ratio of 3.4, comparable value to related works in this area, and throughput of 28 MPixel/s (224 Mbit/s). Taking advantage of images nature, its compression can be parallelized through simultaneous multi-cores compressors. For example, using 5 cores, this work is able to compress those images in a rate of 142 MPixel/s (1.1 Gbit/s). All these features make it useful and effective in a current remote sensing imaging system. / A quantidade de dados gerados e transmitidos pelos satélites para as estações na Terra é cada vez maiores. Com o passar do tempo e avanço da tecnologia, os sistemas de imageamento espaciais, particularmente as missões de observação da Terra, tem utilizado equipamentos com resoluções cada vez maiores. Por esse motivo, se faz necessário garantir que os dados cheguem ao destino de maneira confiável. Dentre algumas técnicas envolvidas, a compressão de dados é o meio mais viável de alcançar esse requisito. Um sistema de compressão de dados para esse fim deve obedecer algumas condições, principalmente quanto ao desempenho. Nesse contexto, implementações em hardware baseadas em predição e codificação de Golomb-Rice têm obtido excelentes resultados considerando desempenho do hardware e da compressão, tanto nos casos sem perdas como nos com perdas. O presente trabalho apresenta uma proposta de hardware digital de um compressor sem perdas para imagens de satélite baseado em predição e codificação Golomb-Rice que busca um balanceamento entre os requisitos de desempenho e a propagação de erros, um problema comum no âmbito de sistemas espaciais e que é potencializado no caso dos compressores de dados. Para validação e análise do compressor, é seguida uma metodologia de verificação funcional de hardware digital e o desenvolvimento de um protótipo em FPGA. Dado um conjunto de imagens do satélite CBERS-2B disponibilizadas pelo Instituto Nacional de Pesquisas Espaciais, os resultados obtidos em FPGA mostram que esse compressor alcança razão de compressão média de 3,4, valor comparável a trabalhos correlatos, e velocidade de 28 MPixel/s (224 Mbit/s). Considerando a natureza das imagens, a compressão pode ser paralelizada por meio de simultâneos núcleos compressores em uma abordagem multicore. Por exemplo, usando 5 núcleos, o sistema proposto é capaz de comprimir essas imagens em uma velocidade de 142 MPixel/s (1.1 Gbit/s). Todas essas características tornam-no útil e efetivo para a aplicação em um sistema moderno de imageamento para sensoriamento remoto.

The goal of this thesis is to analyze and to find solutions of optimization problems derived from automation of functional verification of hardware using artificial neural networks. Verification of any integrated circuit (so called Design Under Verification, DUV) using technique called coverage-driven verification and universal verification methodology (UVM) is carried out by sending stimuli inputs into DUV. The verification environment continuously monitors percentual coverage of DUV functionality given by the specification. In current context, coverage stands for measurable property of DUV, like count of verified arithemtic operations or count of executed lines of code. Based on the final coverage, it is possible to determine whether the coverage of DUV is high enough to declare DUV as verified. Otherwise, the input stimuli set needs to change in order to achieve higher coverage. Current trend is to generate this set by technique called constrained-random stimulus generation. We will practice this technique by using pseudorandom program generator (PNG). In this paper, we propose multiple solutions for following two optimization problems. First problem is ongoing modification of PNG constraints in such a way that the DUV can be verified by generated stimuli as quickly as possible. Second one is the problem of seeking the smallest set of stimuli such that this set verifies DUV. The qualities of the proposed solutions are verified on 32-bit application-specific instruction set processors (ASIPs) called Codasip uRISC and Codix Cobalt.

The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.

Při vývoji současných číslicových systémů, např. vestavěných systému a počítačového hardware, je nutné hledat postupy, jak zvýšit jejich spolehlivost. Jednou z možností je zvyšování efektivity a rychlosti verifikačních procesů, které se provádějí v raných fázích návrhu. V této dizertační práci se pozornost věnuje verifikačnímu přístupu s názvem funkční verifikace. Je identifikováno několik výzev a problému týkajících se efektivity a rychlosti funkční verifikace a ty jsou následně řešeny v cílech dizertační práce. První cíl se zaměřuje na redukci simulačního času v průběhu verifikace komplexních systémů. Důvodem je, že simulace inherentně paralelního hardwarového systému trvá velmi dlouho v porovnání s během v skutečném hardware. Je proto navrhnuta optimalizační technika, která umisťuje verifikovaný systém do FPGA akcelerátoru, zatím co část verifikačního prostředí stále běží v simulaci. Tímto přemístěním je možné výrazně zredukovat simulační režii. Druhý cíl se zabývá ručně připravovanými verifikačními prostředími, která představují výrazné omezení ve verifikační produktivitě. Tato režie však není nutná, protože většina verifikačních prostředí má velice podobnou strukturu, jelikož využívají komponenty standardních verifikačních metodik. Tyto komponenty se jen upravují s ohledem na verifikovaný systém. Proto druhá optimalizační technika analyzuje popis systému na vyšší úrovni abstrakce a automatizuje tvorbu verifikačních prostředí tím, že je automaticky generuje z tohoto vysoko-úrovňového popisu. Třetí cíl zkoumá, jak je možné docílit úplnost verifikace pomocí inteligentní automatizace. Úplnost verifikace se typicky měří pomocí různých metrik pokrytí a verifikace je ukončena, když je dosažena právě vysoká úroveň pokrytí. Proto je navržena třetí optimalizační technika, která řídí generování vstupů pro verifikovaný systém tak, aby tyto vstupy aktivovali současně co nejvíc bodů pokrytí a aby byla rychlost konvergence k maximálnímu pokrytí co nejvyšší. Jako hlavní optimalizační prostředek se používá genetický algoritmus, který je přizpůsoben pro funkční verifikaci a jeho parametry jsou vyladěny pro tuto doménu. Běží na pozadí verifikačního procesu, analyzuje dosažené pokrytí a na základě toho dynamicky upravuje omezující podmínky pro generátor vstupů. Tyto podmínky jsou reprezentovány pravděpodobnostmi, které určují výběr vhodných hodnot ze vstupní domény. Čtvrtý cíl diskutuje, zda je možné znovu použít vstupy z funkční verifikace pro účely regresního testování a optimalizovat je tak, aby byla rychlost testování co nejvyšší. Ve funkční verifikaci je totiž běžné, že vstupy jsou značně redundantní, jelikož jsou produkovány generátorem. Pro regresní testy ale tato redundance není potřebná a proto může být eliminována. Zároveň je ale nutné dbát na to, aby úroveň pokrytí dosáhnutá optimalizovanou sadou byla stejná, jako u té původní. Čtvrtá optimalizační technika toto reflektuje a opět používá genetický algoritmus jako optimalizační prostředek. Tentokrát ale není integrován do procesu verifikace, ale je použit až po její ukončení. Velmi rychle odstraňuje redundanci z původní sady vstupů a výsledná doba simulace je tak značně optimalizována.