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Městská památková rezervace Kroměříž – architektonicko–urbanistické řešení vybrané lokality / Conservation Area Kroměříž - architecture–urban design of the selected siteDočekalová, Pavla January 2014 (has links)
The master's thesis describes the design of urban interior street Vejvanovského in urban conservation Kroměříž and operational and functional adaptations street stalls in the context of surrounding roads and spaces. As part is design of architectural studies for three new objects. Objects respond to the needs, space, matter, and the street and the surroundins. The plots of selected street is designed gallery, hotel with restaurant and city market.
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Fault Modeling and Analysis for FinFET SRAM ArraysMeenakshi Siddharthan, Rathna Keerthi 11 October 2013 (has links)
No description available.
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Power Module Design and Protection for Medium Voltage Silicon Carbide DevicesLyu, Xintong 29 September 2021 (has links)
No description available.
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Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-TechnologieBaldauf, Tim 10 January 2014 (has links)
Die kontinuierliche Skalierung der planaren MOSFETs war in den vergangenen 40 Jahren der Schlüssel, um die Bauelemente immer kleiner und leistungsfähiger zu gestalten. Hinzu kamen Techniken zur mechanischen Verspannung, Verfahren zur Kurzzeitausheilung, die in-situ-dotierte Epitaxie und neue Materialien, wie das High-k-Gateoxid in Verbindung mit Titannitrid als Gatemetall. Jedoch erschwerten Kurzkanaleffekte und eine zunehmende Streuung der elektrischen Eigenschaften die Verkleinerung der planaren Transistoren erheblich. Somit gelangten die planaren MOSFETs mit der aktuellen 28 nm-Technologie teilweise an die Grenzen ihrer Funktionalität. Diese Arbeit beschäftigt sich daher mit der Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie, welche eine bessere Steuerfähigkeit des Gatekontaktes aufweisen und somit die Fortführung der Skalierung ermöglichen. Zudem standen die Anforderungen eines stabilen und kostengünstigen Herstellungsprozesses als Grundvoraussetzung zur Übernahme in die Volumenproduktion stets mit im Vordergrund. Die Simulationen der Tri-Gate-Transistoren stellten dabei den ersten Schritt hin zu einer Multi-Gate-Technologie dar. Ihre Prozessabfolge unterscheidet sich von den planaren Transistoren nur durch die Formierung der Finnen und bietet damit die Möglichkeit eines hybriden 22 nm-Prozesses. Am Beispiel der Tri-Gate-Transistoren wurden zudem die Auswirkungen der Kristallorientierung, der mechanischen Verspannung und der Überlagerungseffekte es elektrischen Feldes auf die Leistungsfähigkeit von Multi-Gate-Strukturen analysiert. Im nächsten Schritt wurden Transistoren mit vollständig verarmten Kanalgebieten untersucht. Sie weisen aufgrund einer niedrigen Kanaldotierung eine Volumeninversion, eine höhere Ladungsträgerbeweglichkeit und eine geringere Anfälligkeit gegenüber der zufälligen Dotierungsfluktuation auf, welche für leistungsfähige Multi-Gate-Transistoren entscheidende Kriterien sind. Zu den betrachteten Varianten zählen die planaren ultradünnen SOI-MOSFETs, die klassischen FinFETs mit schmalen hohen Finnen und die vertikalen Nanowire-Transistoren. Anschließend wurden die Vor- und Nachteile der verschiedenen Transistorstrukturen für eine mittel- bis langfristige industrielle Nutzung betrachtet. Dazu erfolgte eine Analyse der statistischen Schwankungen und eine Skalierung hin zur 14 nm-Technologie. Eine Zusammenfassung aller Ergebnisse und ein Ausblick auf die mögliche Übernahme der Konzepte in die Volumenproduktion schließen die Arbeit ab.:Symbol- und Abkürzungsverzeichnis
1 Einleitung
2 Grundlagen und Entwicklung der CMOS-Technologie
2.1 Planare Transistoren
2.1.1 Theoretische Grundlagen von MOSFETs
2.1.2 Skalierung und Kurzkanalverhalten planarer Transistoren
2.1.3 Mechanische Verspannung von Silizium
2.1.4 Techniken zur mechanischen Verspannung
2.2 Multi-Gate-Transistoren
2.2.1 Multi-Gate-Strukturen
2.2.2 Überlagerungseffekte
2.2.3 Quanteneffekte
2.3 Stand der Technik
3 Grundlagen der Simulation
3.1 Prozesssimulation
3.1.1 Abscheiden und Abtragen von Schichten
3.1.2 Implantation
3.1.3 Thermische Ausheilung mit Diffusion
3.2 Bauelementesimulation
3.2.1 Grundgleichungen und Ladungsträgertransport
3.2.2 Bandlückenverengung
3.2.3 Generation und Rekombination
3.2.4 Ladungsträgerbeweglichkeit
3.2.5 Effekte der mechanischen Verspannung
3.2.6 Ladungsträgerquantisierung
3.3 Kalibrierung der Modellparameter
3.3.1 Prozessparameter
3.3.2 Modellparameter
4 Planare Transistoren auf Basis einer 22 nm-Technologie
4.1 Transistoraufbau
4.1.1 Replacement-Gate-Prozess
4.1.2 In-situ-dotierte Source-Drain-Gebiete
4.1.3 Haloimplantation
4.1.4 Elemente der mechanischen Verspannung
4.2 Charakterisierung des elektrischen Verhaltens
4.2.1 Stationäres Verhalten
4.2.2 Gatesteuerung und Kurzkanaleffekte
4.2.3 Dynamisches Verhalten
5 Tri-Gate-Transistoren
5.1 Prozessintegration und Transistoraufbau
5.1.1 Anforderungen an hochintegrierte Schaltkreise
5.1.2 Hybride CMOS-Technologie
5.1.3 Strukturierung der Finne
5.1.4 Geometrieabhängiges Dotierungsprofil
5.2 Charakterisierung des elektrischen Verhaltens
5.2.1 Stationäres Verhalten
5.2.2 Kurzkanaleffekte und Gatesteuerung
5.2.3 Eckeneffekt
5.2.4 Eckenimplantation
5.2.5 Finnengeometrie
5.2.6 Dynamisches Verhalten
5.3 Optimierung der Tri-Gate-Struktur
5.3.1 Gestaltung der epitaktischen Source-Drain-Gebiete
5.3.2 Mechanisch verspanntes Isolationsoxid
5.3.3 Substratorientierung
6 Transistoren mit vollständig verarmtem Kanal
6.1 Ultra-Dünne-SOI-MOSFETs
6.1.1 Prozessintegration
6.1.2 Charakterisierung des elektrischen Verhaltens
6.2 FinFETs
6.2.1 Prozessintegration
6.2.2 Charakterisierung des elektrischen Verhaltens
6.3 Vertikale Nanowire-MOSFETs
6.3.1 Prozessintegration
6.3.2 Strukturierung des Aktivgebiets
6.3.3 Charakterisierung des elektrischen Verhaltens
6.3.4 Asymmetrisches Dotierungsprofil
6.3.5 Mechanische Verspannung
7 Skalierung und statistische Schwankungen der Strukturen
7.1 Skalierung zur 14 nm-Technologie
7.1.1 Leistungsfähigkeit
7.1.2 Kurzkanalverhalten und Steuerfähigkeit
7.2 Statistische Schwankungen
7.2.1 Impedanz-Feld-Methode
7.2.2 Zufällige Dotierungsfluktuation
7.2.3 Fixe Ladungen im Oxid
7.2.4 Metall-Gate-Granularität
7.2.5 Geometrische Variationen
7.2.6 Kombination der Störquellen
8 Zusammenfassung und Ausblick
Anhang
Literaturverzeichnis
Danksagung
Acknowledgement / Within the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work.:Symbol- und Abkürzungsverzeichnis
1 Einleitung
2 Grundlagen und Entwicklung der CMOS-Technologie
2.1 Planare Transistoren
2.1.1 Theoretische Grundlagen von MOSFETs
2.1.2 Skalierung und Kurzkanalverhalten planarer Transistoren
2.1.3 Mechanische Verspannung von Silizium
2.1.4 Techniken zur mechanischen Verspannung
2.2 Multi-Gate-Transistoren
2.2.1 Multi-Gate-Strukturen
2.2.2 Überlagerungseffekte
2.2.3 Quanteneffekte
2.3 Stand der Technik
3 Grundlagen der Simulation
3.1 Prozesssimulation
3.1.1 Abscheiden und Abtragen von Schichten
3.1.2 Implantation
3.1.3 Thermische Ausheilung mit Diffusion
3.2 Bauelementesimulation
3.2.1 Grundgleichungen und Ladungsträgertransport
3.2.2 Bandlückenverengung
3.2.3 Generation und Rekombination
3.2.4 Ladungsträgerbeweglichkeit
3.2.5 Effekte der mechanischen Verspannung
3.2.6 Ladungsträgerquantisierung
3.3 Kalibrierung der Modellparameter
3.3.1 Prozessparameter
3.3.2 Modellparameter
4 Planare Transistoren auf Basis einer 22 nm-Technologie
4.1 Transistoraufbau
4.1.1 Replacement-Gate-Prozess
4.1.2 In-situ-dotierte Source-Drain-Gebiete
4.1.3 Haloimplantation
4.1.4 Elemente der mechanischen Verspannung
4.2 Charakterisierung des elektrischen Verhaltens
4.2.1 Stationäres Verhalten
4.2.2 Gatesteuerung und Kurzkanaleffekte
4.2.3 Dynamisches Verhalten
5 Tri-Gate-Transistoren
5.1 Prozessintegration und Transistoraufbau
5.1.1 Anforderungen an hochintegrierte Schaltkreise
5.1.2 Hybride CMOS-Technologie
5.1.3 Strukturierung der Finne
5.1.4 Geometrieabhängiges Dotierungsprofil
5.2 Charakterisierung des elektrischen Verhaltens
5.2.1 Stationäres Verhalten
5.2.2 Kurzkanaleffekte und Gatesteuerung
5.2.3 Eckeneffekt
5.2.4 Eckenimplantation
5.2.5 Finnengeometrie
5.2.6 Dynamisches Verhalten
5.3 Optimierung der Tri-Gate-Struktur
5.3.1 Gestaltung der epitaktischen Source-Drain-Gebiete
5.3.2 Mechanisch verspanntes Isolationsoxid
5.3.3 Substratorientierung
6 Transistoren mit vollständig verarmtem Kanal
6.1 Ultra-Dünne-SOI-MOSFETs
6.1.1 Prozessintegration
6.1.2 Charakterisierung des elektrischen Verhaltens
6.2 FinFETs
6.2.1 Prozessintegration
6.2.2 Charakterisierung des elektrischen Verhaltens
6.3 Vertikale Nanowire-MOSFETs
6.3.1 Prozessintegration
6.3.2 Strukturierung des Aktivgebiets
6.3.3 Charakterisierung des elektrischen Verhaltens
6.3.4 Asymmetrisches Dotierungsprofil
6.3.5 Mechanische Verspannung
7 Skalierung und statistische Schwankungen der Strukturen
7.1 Skalierung zur 14 nm-Technologie
7.1.1 Leistungsfähigkeit
7.1.2 Kurzkanalverhalten und Steuerfähigkeit
7.2 Statistische Schwankungen
7.2.1 Impedanz-Feld-Methode
7.2.2 Zufällige Dotierungsfluktuation
7.2.3 Fixe Ladungen im Oxid
7.2.4 Metall-Gate-Granularität
7.2.5 Geometrische Variationen
7.2.6 Kombination der Störquellen
8 Zusammenfassung und Ausblick
Anhang
Literaturverzeichnis
Danksagung
Acknowledgement
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A Fpga-based Architecture For Led Backlight DrivingZheng, Zhaoshi 01 January 2010 (has links)
In recent years, Light-emitting Diodes (LEDs) have become a promising candidate for backlighting Liquid Crystal Displays [1] (LCDs). Compared with traditional Cold Cathode Fluorescent Lamps (CCFLs) technology, LEDs offer not only better visual quality, but also improved power efficiency. However, to fully utilized LEDs' capability requires dynamic independent control of individual LEDs, which remains as a challenging topic. A FPGA-based hardware system for LED backlight control is proposed in this work. We successfully achieve dynamic adjustment of any individual LED's intensity in each of the three color channels (Red, Green and Blue), in response to a real time incoming video stream. In computing LED intensity, four video content processing algorithms have been implemented and tested, including averaging, histogram equalization, LED zone pattern change detection and non-linear mapping. We also construct two versions of the system. The first employs an embedded processor which performs the above-mentioned algorithms on pre-processed video data; the second embodies the same functionality as the first on fixed hardware logic for better performance and power efficiency. The system servers as the backbone of a consolidated display, which yields better visual quality than common commercial displays, we build in collaboration with a group of researchers from CREOL at UCF.
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EMI Suppression and Performance Enhancement for Truly Differential Gate DriversMiranda-Santos, Jesi 30 June 2023 (has links)
The increasing market demand for wideband gap (WBG) power switches has led to heightened competition to increase converter power density, switching frequencies, and reduce form factor, among other factors. However, this technology has also brought about an increase in encounters with electromagnetic interference (EMI), posing significant challenges. Nevertheless, the maturation of power switches has been accompanied by an improvement in gate drive technology aimed at resolving EMI challenges, albeit at a higher component and cost expense. This thesis aims to design, analyze, and implement a recent innovative differential gate driver for a 1.2 kV SiC MOSFET full bridge module. The purpose of this design is to mitigate EMI, improve performance, and reduce the number of filtering elements that are typically required. The investigation into the impact of EMI on electrical systems involves exploring factors such as testing equipment, power supplies, and gate drive layout. Based on these considerations, system and sub-system level analyses are conducted to derive practical design recommendations for implementing the differential gate driver. Three gate drive PCBs are designed and evaluated through extensive double pulse tests (DPTs). Furthermore, continuous switching of the driver presents its own set of challenges that are not apparent during the DPTs, requiring further exploration of low-cost solutions. Finally, a comparison between custom and discrete module solutions employing 1.2 kV SiC MOSFETs is conducted, highlighting the advantages and disadvantages of each approach. The solutions proposed in this work are intended to be extended to other gate drive ICs, with the goal of providing valuable insights and guidelines for EMI suppression and gate driver performance enhancement. / Master of Science / The increasing demand for powerful and efficient electronic devices has led to competition to develop better converters with wideband gap (WBG) power switches. These switches can make electronics work faster and take up less space, but they can also cause electromagnetic interference (EMI) that can be problematic. Despite these challenges, advances in power switch technology have led to improvements in gate drive technology, which can help reduce EMI, albeit, sometimes, at a higher cost. This research aims to design and analyze an innovative differential gate driver for a 1.2 kV SiC MOSFET full bridge module that can help mitigate EMI, improve performance, and reduce the number of required filtering elements. A system-level analysis is conducted to identify critical noise paths and potential solutions in response to poor gate driver performance. Practical design recommendations are provided for implementing a differential gate driver, and three PCB designs are tested and evaluated to showcase the effectiveness of the proposed solutions. The work also includes a comparison between a custom module and discrete module solutions employing 1.2 kV SiC MOSFETs, highlighting the advantages and disadvantages of each approach. The findings are extended to other gate drivers that share similar performance specifications, demonstrating the potential and improvements that can be achieved with the suggested techniques. Overall, the study provides valuable insights and guidelines for EMI suppression and performance enhancement in power electronics systems utilizing differential gate drivers.
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Implementation and Performance of an Improved Turbo Decoder on a Configurable Computing MachinePuckett, W. Bruce 20 July 2000 (has links)
Turbo codes are a recently discovered class of error correction codes that achieve near-Shannon limit performance. Because of their complexity and highly parallel nature, turbo-coded applications are well suited for configurable computing. Field-programmable gate arrays (FPGAs), which are the main building blocks of configurable computing machines (CCMs), allow users to design flexible hardware that is optimized for performance, speed, power consumption, and chip-area. This thesis presents the implementation and performance of an improved turbo decoder on a configurable computing platform. The design's performance and throughput are emphasized in light of its algorithmic improvements, and its flexibility is emphasized as it is ported to a newer, more efficient architecture with more hardware resources. Because this decoder will eventually become the error correction component of a software radio, the design must maintain a high data rate, interface easily with other modules, and conserve hardware resources for future research developments. / Master of Science
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Literature Review on the Use of Nucleic Acid-Based Logic Gates for the Detection of Human DiseasesBlanco Martinez, Enrique J 01 January 2017 (has links)
Conventional methods for diagnosis of human disease are, at times, limited in different regards including time requirement, either experimental or data processing, sensitivity, and selectivity. It is then that a Point of Care Criteria, which considers the true utility and usefulness of the device, is employed to propose new diagnostic devices capable of overcoming the aforementioned shortcomings of conventional tools. Nucleic acid, characterized for its predictable base-pairing nature, is considered to be a highly-selective, yet greatly modifiable device. Its behavior is then described through Boolean Logic, where “true” or “false” outputs are mathematically described as “1” and “0”, respectively. This mathematical approach is then referred to as Logic Gates, where outputs can be predicted based on satisfied environmental conditions. The mechanisms, capable of exhibiting Logic Gate behavior, are described.
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MACRO BASED COMPILER FOR A PARTIALLY RECONFIGURABLE COMPUTERHANDA, MANISH January 2002 (has links)
No description available.
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Reconfigurable wavelet-based architecture for pattern recognition applications using a field programmable gate arrayAl-aqeeli, Abulqadir January 1998 (has links)
No description available.
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