Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (M.S.)--Baylor University, 2006. / Includes bibliographical references (p. 48).

Techn. Universiẗat, Diss., 2003--Berlin.

University, Diss., 2004--Heidelberg.

Thesis (Ph. D.)--Lehigh University, 2006. / Includes vita. Includes bibliographical references (leaves 121-133).

Thesis (M.S.)--University of Texas at Dallas, 2008. / Includes vita. Includes bibliographical references (leaves 74-75)

Λαμβάνοντας υπόψη τις υπηρεσίες (βασικές και ειδικές) που πρέπει να διαθέτει ένας πρότυπος ιστότοπος πολιτιστικού περιεχομένου και με βάση τα κριτήρια ποιότητας τα οποία αναλύθηκαν στο αντίστοιχο παραδοτέο η παρούσα αναφορά αξιολογεί ενδεικτικά ένα τυχαία επιλεγμένο σύνολο ιστοτόπων πολιτισμού από την Ελλάδα και το εξωτερικό. Επίσης, εξειδικεύει την αξιολόγηση και στις εκπαιδευτικές εφαρμογές και υπηρεσίες που παρέχουν οι συγκεκριμένοι ιστότοποι στον τελικό χρήστη. Τέλος, παραθέτει έναν συνοπτικό πίνακα αποτελεσμάτων. / Taking into consideration the services (basic and special) that a model internet gate with educational content should contains and having in mind the quality criteria which were analyzed in corresponding deliverable, the present report evaluates indicatively an accidentally selected total of cultural internet gates from Greece and the abroad. Also, it specialises the evaluation in the educational applications and services that the specific internet gates provide in the final user. Finally, it mentions a concise table of results.

Reductions in the cost and size of integrated circuits are allowing more and more complex functions to be included in previously simple tools such as lawn-mowers, ovens, and thermostats. Because of this, the process of synthesizing such functions from their initial representation to an optimal VLSI implementation is rarely hand-performed; instead, automated synthesis and optimization tools are a necessity. The factors such tools must take into account are numerous, including area (size), power consumption, and timing factors, to name just a few. Existing tools have traditionally focused upon optimization of two-level representations. However, new technologies such as Field Programmable Gate Arrays (FPGAs) have generated additional interest in three-level representations and structures such as Kronecker Decision Diagrams (KDDs). The reason for this is that when implementing a circuit on an FPGA, the cost of implementing exclusive-or logic is no more than that of traditional AND or OR gates. This dissertation investigates the use of the autocorrelation coefficients in logic synthesis for these types of structures; specifically, whether it is possible to pre-process a function to produce a subset of its autocorrelation coefficients and make use of this information in the choice of a three-level decomposition or of decomposition types within a KDD. This research began as a general investigation into the properties of autocorrelation coefficients of switching functions. Much work has centered around the use of a function's spectral coefficients in logic synthesis; however, very little work has used a function's autocorrelation coefficients. Their use has been investigated in the areas of testing, optimization for Programmable Logic Arrays (PLAs), identification of types of complexity measures, and in various DD-related applications, but in a limited manner. This has likely been due to the complexity in their computation. In order to investigate the uses of these coefficients, a fast computation technique was required, as well as knowledge of their basic properties. Both areas are detailed as part of this work, which demonstrates that it is feasible to quickly compute the autocorrelation coefficients. With these investigations as a foundation we further apply the autocorrelation coefficients to the development of a classification technique. The autocorrelation classes are similar to the spectral classes, but provide significantly different information. The dissertation demonstrates that some of this information highlighted by the autocorrelation classes may allow for the identification of exclusive-or logic within the function or classes of functions. In relation to this, a major contribution of this work involves the design and implementation of algorithms based on these results. The first of these algorithms is used to identify three-level decompositions for functions, and the second to determine decomposition type lists for KDD-representations. Each of these implementations compares well with existing tools, requiring on average less than one second to complete, and performing as well as the existing tools about 70% of the time. / Graduate

This thesis is on the study of the characterization of interfaces and surfaces of high-k stacks for the future microelectronics. The changes of the high-k stacks during thermal processing and its mechanism have been experimentally investigated by high-resolution Rutherford Backscattering Spectrometry (HRBS) in combination with isotope tracing. The experimental results are consistent with the theoretical prediction that the silicon will be emitted outward to release the stress which is induced by the interface Si oxidation. Then, we studied the potential method, oxygen-gettering by Ti overlayer, for controlling the interface SiO2 thickness. Furthermore, we proposed a Time-Of-Flight (TOF) detector system for application on crystallographic analysis. TOF-RBS system is capable to analyze the sample’s crystallographic and chemical information even at the near surface of the sample, which is strongly required by the future microelectronics industry. In this chapter, brief introduction to the high-k stacks and the outline of this thesis are described. / Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第13814号 / 工博第2918号 / 新制||工||1431(附属図書館) / 26030 / UT51-2008-C730 / 京都大学大学院工学研究科マイクロエンジニアリング専攻 / (主査)教授 木村 健二, 教授 斧 髙一, 教授 立花 明知 / 学位規則第4条第1項該当

Threshold logic gates gaining more importance in recent years due to the significant development in the switching devices. This renewed the interest in synthesis and testing of circuits with threshold logic gates. Two important synthesis considerations of threshold logic circuits are addressed namely, threshold logic function identification and reducing the total number of threshold logic gates required to represent the given boolean circuit description. A fast method to identify the given Boolean function as a threshold logic function with weight assignment is introduced. It characterizes the threshold logic function based on the modified chows parameters which results in drastic reduction in time and complexity. Experiment results shown that the proposed method is at least 10 times faster for each input and around 20 times faster for 7 and 8 input, when comparing with the algorithmic based methods. Similarly, it is 100 times faster for 8 input, when comparing with asummable method. Existing threshold logic synthesis methods decompose the larger input functions into smaller input functions and perform synthesis for them. This results in increase in the number of threshold logic gates required to represent the given circuit description. The proposed implicit synthesis methods increase the size of the functions that can be handled by the synthesis algorithm, thus the number of threshold logic gates required to implement very large input function decreases. Experiment results shown that the reduction in the TLG count is 24% in the best case and 18% on average. An automatic test pattern generation approach for transition faults on a circuit consisting of current mode threshold logic gates is introduced. The generated pattern for each fault excites the maximum propagation delay at the gate (the fault site). This is a high quality ATPG. Since current mode threshold logic gate circuits are pipelined and the combinational depth at each pipeline stage is practically one. It is experimentally shown that the fault coverage for all benchmark circuits is approximately 97%. It is also shown that the proposed method is time efficient.