The performance scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over four decades. Addressing the current challenges with CMOS scaling, the 2005 edition of International Technology Roadmap for Semiconductors has predicted the need for so-called technology boosters involving new materials for the gate dielectric and the channel as well as innovative structures. Theoretical studies suggest that the incorporation of high-mobility channel materials such as germanium and III-Vs could outperform bulk Si technology in terms of switching characteristics. Hence, this has recently led to tremendous research activity to explore the prospects of III-V materials for CMOS applications. Nevertheless, technological challenges such as formation of highquality interface between gate dielectric and III-V channel have hindered the demonstration of enhancement-mode III-V MOSFETs. Hence, tremendous effort has been devoted to study the exact origin of Fermi level pinning at the oxide/III-V interface. On the other hand, the advent of high-k materials has opened up the possibility of exploring new channel materials, for which it is challenging to achieve high-quality interface analogous to that of SiO2 on Si. Lately, III-Vs have been extensively explored in order to find compatible gate dielectrics which can unpin the Fermi level at the interface. Amongst various schemes, atomic layer deposition of high-k dielectrics offers some unique advantages such as reduction of GaAs interfacial oxides upon high-k deposition through an appropriate choice of precursor chemistry. The chief focus of this dissertation is to develop a simple wet clean process prior to high-k deposition, suitable for III-V substrates. The impact of various chemical treatments of GaAs substrates on the properties of high-k/GaAs interface was studied through extensive material and electrical characterization methods. The suitability of the ALD-grown high-k gate dielectrics on GaAs for MOSFET fabrication was explored. Charge trapping was found to result in significant errors in mobility extraction in high-k GaAs interface, where the role of high-k is not well understood. Hence, pulsed I-V and QV measurements and galvanomagnetic effects were utilized in order to directly measure the inversion charge in the channel without being affected by the charge traps as much as possible. It was also found that the material studies on GaAs substrates can be readily extended to other III-V channels, such as InGaAs. / text

This document details experiments attempting to increase the performance of metal-oxide-semiconductor field-effect-transistors (MOSFETs) which are the mainstay of the semiconductor industry. Replacing the silicon channel with an ultra-thin epitaxial germanium layer grown selectively on a silicon (100) bulk wafer is examined in detail. The gate oxide chosen for the germanium devices is a high-k gate oxide, HfO2, and the gate electrode is a metal gate, tantalum-nitride. They demonstrate large improvements in drive current and mobility over identically processed silicon PMOSFETs. In addition to the planar germanium PMOSFETs, a process has been developed for 50nm and smaller germanium P-finFETs and N and P germanium tunnel-FETs. The patterning of sub-30nm wide and 230nm tall three dimensional fins has been done with electron beam lithography and dry plasma etching. The processes to deposit high-k gate oxide and metal gates on the sub-30nm wide fins have been developed. All that remains for the production of these devices is electron beam lithography with a maximum misalignment error of 40nm. / text

In today's world, it is becoming increasingly important to be able to design high performance integrated circuits (ICs) and have them run at as low power as possible. Gate sizing and threshold voltage (Vt) assignment optimizations are one of the major contributors to such trade-offs for power and performance of ICs. In fact, the ever increasing design sizes and more aggressive timing requirements make gate sizing and Vt assignment one of the most important CAD problems in physical synthesis. A promising gate sizing optimization algorithm has to satisfy requirements like being scalable to tackle very large design sizes, being able to optimally utilize a large (but finite) number of possible gate configurations available in standard cell library based on different gate sizes and/or threshold voltages (Vt) and/or gate lengths (Lg), and also, being able to handle non-convex cell delays in modern cell libraries. The work in this thesis makes use of the research-oriented infrastructure made available as part of the ISPD (International Symposium on Physical Design) 2012 Gate Sizing Contest that addresses the issues encountered in modern gate sizing problems. We present a two-phase optimization approach where Lagrangian Relaxation is used to formulate the optimization problem. In the first phase, the Lagrangian relaxed subproblem is iteratively solved using a greedy algorithm, while in the second phase, a cell downsizing and Vt upscaling heuristic is employed to further recover power from the timing-feasible and power-optimized sizing solution obtained at the end of first phase. We also propose a multi-core implementation of the first-phase optimizations, which constitute majority of the total runtime, to take advantage of multi-core processors available today. A speedup of the order of 4 to 9 times is seen on different benchmarks as compared to serial implementation when run on a 2 socket 6-core machine. Compared to the winner of ISPD 2012 contest, we further reduce leakage power by 17.21% and runtime by 87.92%, on average, while obtaining feasible sizing solutions on all the benchmark designs. / text

Compared with its inorganic counterpart, organic thin-film transistor (OTFT) has advantages such as low-temperature fabrication, adaptability to large-area flexible substrate, and low cost. However, they usually need high operating voltage and thus are not suitable for portable applications. Although reducing their gate–dielectric thickness can lower the operating voltage, it increases their gate leakage. A better way is making use of high-κ gate dielectric, which is the main theme of this research. Firstly, pentacene OTFTs with HfO2 gate dielectric nitrided in N2O or NH3 at 200 oC were studied. The NH3-annealed OTFT displayed higher carrier mobility, larger on/off current ratio, smaller sub-threshold swing and smaller Hooge?s parameter than the N2O-annealed device. All these advantages were attributed to more nitrogen incorporation at the dielectric surface by the NH3 annealing which provided stronger passivation of surface traps. The incorporation of lanthanum to hafnium oxide was demonstrated to realize enhanced interface in the pentacene OTFTs. Therefore, pentacene OTFTs with HfLaO gate dielectric annealed in N2, NH3, O2 or NO at 400 oC were investigated. Among the 4 devices, the NH3-annealed OTFT obtained the highest carrier mobility, smallest sub-threshold swing and smallest 1/f noise. All these should be attributed to the improved interface between the gate dielectric and the organic semiconductor associated with the passivation effects of the NH3 annealing on the dielectric surface. The processing temperature of OTFTs is a big concern because use of flexible or glass substrate is the trend in organic electronics. Therefore, the HfLaO gate dielectric was annealed in N2, NH3, or O2 at two different temperatures, 200 oC and 400 oC. For all the annealing gases, the OTFTs annealed at 400 oC achieved higher carrier mobility, which could be supported by SEM image that pentacene tended to form larger grains (thus less carrier scattering) on HfLaO annealed at 400 oC. Furthermore, the HfLaO film annealed at 400 oC achieved much smaller leakage because more thermal energy at higher annealing temperature could remove oxide defects more effectively. Fluorination of the HfLaO film (annealed in N2 or NH3 at 400 oC) in a plasma based on CHF3 and O2 was also proposed. For both annealing gases, the OTFT with a 100-s plasma treatment achieved higher carrier mobility and smaller 1/f noise than that without plasma treatment. All these improvements should be due to fluorine incorporation at the dielectric surface which passivated the traps there. By contrast, for longer time (300 s or 900 s) of plasma treatment, the performance of the OTFTs deteriorated due to damage of dielectric surface induced by excessive plasma treatment. Lastly, a comparative study was done on pentacene OTFTs with HfLaO or La2O3 as gate dielectric. For the same annealing gas (H2, N2, NH3, or O2 at 400 oC), the OTFT with La2O3 gate dielectric obtained lower carrier mobility, smaller on/off current ratio, and larger threshold voltage than that based on HfLaO. The worse performance of the OTFTs with La2O3 gate dielectric was due to the degradation of La2O3 film caused by moisture absorption. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / A field programmable gate array (FPGA) is used to decode Inter-Range Instrumentation Group (IRIG) time code for a PC-based Time-Space-Position Information (TSPI) acquisition. The FPGA architecture can latch time via an external event trigger or a programmable periodic internal event. By syncing time with an external IRIG Group Type B (IRIG-B) signal and using an 8 megahertz (MHz) internal clock, captured time has 125 nanosecond (ns) precision. A Range Instrumentation Control System (RICS) application utilizing the FPGA design to capture IRIG time is presented and test results show matching time accuracy when compared to commercial IRIG time capture hardware components.

As a result of harmful textile production, sustainability has become the movement by which the apparel industry explores solutions to improve procedures in fashion design to maintain a healthy environment. However, the issue is consumers trust the sustainability claims and marketing materials of apparel products at face value without knowing its environmental impact. The overall purpose of this research was to compare the environmental implications of widely produced and owned apparel products through a life cycle assessment approach. This life cycle assessment study examines key environmental impact categories of the materials and production phase (cradle to gate) of a pair of jeans and a cotton t-shirt. The specific purpose of this study was to identify if the production processes make a sustainable product at the point of purchase. Furthermore, this research study compares the environmental impacts of a denim jean and dyed cotton t-shirt utilizing the ReCipe 2008 LCA tool.

published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

Η μεγάλη εξάπλωση των δικτύων που βασίζονται στο Internet Protocol (IP) , έδωσε την ευκαιρία για χρήση του Διαδικτύου για μετάδοση φωνής , μέσω της τεχνολογίας Voice over IP(VoIP) , έναντι των παραδοσιακών δημοσίων τηλεφωνικών δικτύων (PSTN) . Το Session Initiation Protocol είναι το πρωτόκολλο σηματοδοσίας , που χρησιμοποιείται για τον έλεγχο συνόδων πολυμέσων , όπως κλήσεις φωνής ή βιντεοκλήσεις στα δίκτυα IP . Η χρησιμοποίηση του πρωτοκόλλου σε φορητές συσκευές , όπου η διαχείριση πόρων παίζει σπουδαίο ρόλο , δίνει το ερέθισμα για τη δημιουργία ειδικού υλικού που θα αποφορτίζει τον επεξεργαστή της συσκευής από τους απαιτητικούς ελέγχους που χρειάζονται για την δημιουργία μιας συνόδου . Στα πλαίσια της παρούσας διπλωματικής εργασίας παρουσιάζεται ένα σύστημα , υλοποιημένο σε FPGA , που προσομοιώνει έναν χρήστη SIP , κι έχει τη δυνατότητα να λαμβάνει , να επεξεργάζεται και να απαντά σε μηνύματα για την δημιουργία μια συνόδου . Στα κεφάλαια που ακολουθούν παρουσιάζεται η δομή του πρωτοκόλλου και τα χαρακτηριστικά του συστήματος που υλοποιήθηκε . Αρχικά παρουσιάζονται οι βασικές αρχές του πρωτοκόλλου και τα δομικά στοιχεία του . Έπειτα αναλύεται η δομή ενός SIP μηνύματος κι εξηγούνται οι λόγοι που κάνουν την αποθήκευσή του απαιτητική εργασία για την CPU . Έπειτα αναλύεται η βασική διαδικασία δημιουργίας συνόδου χρησιμοποιώντας ένα παράδειγμα . Το επόμενο μέρος αφιερώνεται στην αναλυτική περιγραφή του συστήματος που υλοποιήθηκε και την διαδικασία ελέγχου της ορθής λειτουργίας του . Τέλος παρουσιάζονται τα αποτελέσματα και συμπεράσματα της εργασίας . / The wide spread of networks based on Internet Protocol (IP), gave the opportunity for using the Internet for voice transmission , through Voice over IP (VoIP) technology, over traditional public telephone networks (PSTN). The Session Initiation Protocol is a signaling protocol , used to control multimedia sessions such as voice calls or video calls in IP networks. The use of this protocol in mobile devices , where resources management is very important ,is giving the stimulus for the creation of special hardware that offloads the CPU of demanding controls needed to create a session . As part of this thesis ,a system implemented on FPGA, which simulates a SIP user, and has the ability to receive, process and respond to messages to create a session , is presented. The following chapters present the structure of the protocol and the characteristics of the implemented system . Originally presented the basic principles of the Protocol and its structural elements . Thereafter the structure of a SIP message is analyzed , and the reasons that make storing a demanding work for the CPU , are explained. Then the basic process of creating a session is analyzed , using an example . The next part is devoted to a detailed description of the implemented system and the process of verifying the proper operation. Finally are presented the results and conclusions of the work .