Includes vita. / Title from PDF of title page. / Document formatted into pages; contains 204 pages. / Thesis (Ph.D.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: The goal of this research project was to contribute to the understanding of CuGaSe2/CdS photovoltaic devices, and to improve the performance of these devices. The initial part of the research dealt with the optimization of a Sequential Deposition process for CuIn(Ga)Se2 absorber formation. As an extension of this, a recipe (Type I Process) for CuGaSe2 absorber layer fabrication was developed, and the deposition parameters were optimized. Electrical characterization of the thin films and completed devices was carried out using techniques such as Two-Probe and Three-Probe Current-Voltage, Capacitance-Frequency, Capacitance-Voltage, and Spectral Response measurements. Structural/chemical characterization was done using XRD and EDS analysis. Current densities of up to 15.2 mA/cm2, and Fill Factors of up to 58% were obtained using the Type I CuGaSe2 Process. VOC's, however, were limited to less than 700 mV. / ABSTRACT: Several process variations, such as changes in the rate/order/temperature of depositions and changes in the thickness of layers, resulted in little improvement. With the aim of breaking through this VOC performance ceiling, a new absorber recipe (Type II Process) was developed. VOC's of up to 735 mV without annealing, and those of up to 775 mV after annealing, were observed. Fill Factors were comparable to those obtained with Type I Process, whereas the Current Densities were found to be reduced (typically, 10-12 mA/cm2, with the best value of 12.6 mA/cm2). This performance of Type II devices was correlated to a better intermixing of the elements during the absorber formation. To gain an understanding of the performance limitations, two simulation techniques, viz. SCAPS and AMPS, were used to model our devices. / ABSTRACT: Several processing experiments and SCAPS modeling indicate that a defective interface between CuGaSe2 and CdS, and perhaps a defective absorber layer, are the cause of the VOC limitation. AMPS simulation studies, on the other hand, suggest that the back contact is limiting the performance. Attempts to change the physical back contact, by changes in the absorber processing, were unsuccessful. Processing experiments and simulations also suggest that the CuGaSe2/CdS solar cell involves a true heterojunction between these two layers. / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.

Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development for commercial applications because of its demonstrated high performance at low processing temperatures. The objective of the research presented in this thesis is to provide detailed assessments of device stability, temperature dependence, and related phenomena for IGZO-based TFTs processed at temperatures between 200 °C and 300 °C. TFTs tested exhibit an almost rigid shift in log₁₀(I[subscript D]) – V[subscript GS] transfer curves in which the turn-on voltage, V[subscript ON], moves to a more positive gate voltage with increasing stress time during constant-voltage bias-stress testing of IGZO TFTs. TFT stability is improved as the post-deposition annealing temperature increases over the temperature range of 200 – 300 ºC. The turn-on voltage shift induced by constant-voltage bias-stressing is at least partially reversible; V[subscript ON] tends to recover towards its initial value of V[subscript ON] if the TFT is left unbiased in the dark for a prolonged period of time and better recovery is observed for a longer recovery period. V[subscript ON] for a TFT can be set equal to zero after bias-stress testing if the TFT electrodes are grounded and the TFT is maintained in the dark for a prolonged period of time. Attempts to accelerate the recovery process by application of a negative gate bias at elevated temperature (i.e., 100 ºC) were unsuccessful, resulting in severely degraded subthreshold swing. An almost rigid log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift to a lower (more negative) V[subscript ON] with increasing temperature is observed in the range of –50 °C to +50 °C, except for a TFT with an initial V[subscript ON] equal to zero, in which case the log₁₀(ID) – V[subscript GS] transfer curve is temperature-independent. A more detailed temperature-dependence assessment, however, indicates that the log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift is not exactly rigid since the mobility is found to increase slightly with increasing temperature. A noticeable anomaly is observed in certain log₁₀(I[subscript D]) – VGS transfer curves, especially when obtained at elevated temperature (e.g., 30 and 50 ºC), in which I[subscript D] decreases precipitously near zero volts in the positive gate voltage sweep. This anomaly is attributed to a gate-voltage-step-involved detrapping and subsequent retrapping of electrons in the accumulation channel and/or channel/gate insulator interface. In fact, all IGZO TFT stability and temperature-dependence trends are attributed to channel interface and/or channel bulk trapping/detrapping. / Graduation date: 2009

Indium-gallium-zinc oxide (IGZO) and zinc-tin oxide (ZTO) are investigated for thin-film transistor (TFT) applications. Negative bias illumination stress (NBIS) is employed for electrical stability assessment. Unpassivated IGZO and ZTO TFTs suffer from severe NBIS instabilities. Zinc-tin-silicon oxide is found to be an effective passivation layer for IGZO and ZTO TFTs, significantly improving the NBIS stability. NBIS instabilities in unpassivated TFTs are attributed to an NBIS-induced desorption of chemisorbed oxygen from the channel layer top surface, exposing surface oxygen vacancies. A ZTSO layer protects the channel layer top surface from adsorbed gas interactions and also appears to reduce the density of oxygen vacancies. The best device architectures investigated with respect to TFT electrical performance are found to be staggered with aluminum electrodes for unpassivated TFTs and coplanar with ITO electrodes for ZTSO-passivated TFTs. Annealing in wet-O₂ is not found to be effective for improving the performance of IGZO or ZTO TFTs or for reducing the post-deposition annealing temperature. / Graduation date: 2012

The incorporation of Gallium Nitride (GaN) Power Amplifiers (PAs) into future high power aperture radar systems is certain; however, the introduction of this technology into multifunction radar systems will present new challenges to radar engineers. This dissertation describes a broad investigation into amplitude and phase transients produced by GaN PAs when they are excited with multifunction radar waveforms. These transients are the result of self-heating electrothermal memory effects and are manifested as interpulse instabilities that can negatively impact the coherent processing of multiple pulses. A behavioral model based on a Foster network topology has been developed to replicate the measured amplitude and phase transients accurately. This model has been used to develop a digital predistortion technique that successfully mitigates the impact of the transients. The Moving Target Indicator (MTI) Improvement Factor and the Root Mean Square (RMS) Pulse-to-Pulse Stability are used as metrics to assess the impact of the transients on radar system performance and to test the effectiveness of a novel digital predistortion concept. / Ph. D.