Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 147-155). Available also in a digital version from Dissertation Abstracts.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 101-108). Available also in a digital version from Dissertation Abstracts.

The continual downscaling of the thickness of the SiO₂ layer in the complementary metal oxide semiconductor (CMOS) transistors has been one of the main driving forces behind the growth of the semiconductor industry for past 20-30 years. The gate dielectric works as a capacitor and therefore the reduction in thickness results in increase of capacitance and the speed of the device. However, this process has reached the limit when the further reduction of the SiO₂ thickness will result in a leakage current above the acceptable limit, especially for mobile devices. This problem can be resolved by replacing SiO₂ with materials which have higher dielectric constants (high-k). The leading candidates to replace SiO₂ as a gate material are hafnium dioxide and hafnium silicate. However, several problems arise when using these materials in the device. One of them is to find p and n type gate metals to match with the valence and conduction band edges of silicon. This problem can be rooted in lack of our understanding of the band alignment and its controlling mechanisms between the materials in the gate stack. Theoretical simulations using density functional theory can be very useful to address such problems. In this dissertation present a theoretical study of the band alignment between HfO₂ and SiO₂ interface. We identify oxygen coordination as a governing factor for the band alignment. Next, we discuss effects of Al incorporation on the band alignment at the SiO₂/HfO₂ interface. We find that one can tune the band alignment by controlling the concentration of Al atoms in the stack. We also perform a theoretical study of HfO₂/Metal interface in case of Rh. We identify Rh as a good candidate for a p-type gate metal due to its large work-function and the low oxidation energy. Finally, we report a study of the stability of oxygen vacancies across the gate stack. We model a gate stack composed of n-Si/SiO₂/HO₂/Rh. We find that oxygen vacancies are easier to create in SiO₂ than in HfO₂. Also, vacancies in HfO₂ modify the band alignment, while in SiO₂ they have no effect. / text

Continuing to scale down the transistor size makes the introduction of high-k dielectric necessary. However, there are still a lot of problems with highk transistors such as worse reliability and Fermi-level pinning. In HfO₂, low crystallization temperature, fixed charge in the bulk and low quality of the Si/HfO₂ interface cause reliability problems. Fermi-level pinning results in high threshold voltage. For the first work in this dissertation, forming Hf1-xTaxO through doping HfO₂ with Ta is used to improve the crystallization temperature and electron mobility. Then, the fluorine passivation of high-k dielectrics is studied. With fluorine passivation, the electron mobility was improved in NMOSFETs with gate stacks of poly-Si/TaN/HfO₂/p-Si with thin TaN layers. Inserting a 1.5nm layer of HfSiON between TaN and HfO₂ completely blocked the fluorine atoms so that they could not reach the Si interface. Thus, no mobility was improved even with fluorine implantation. In order to decrease threshold voltage, we must study mechanisms of Fermi level pinning (FLP) in high-k gate stacks. We summarize three FLP mechanisms: (1) the dipole formation at the interface between metal gate and high-k dielectric due to hybridization; 2) the dipole formation through oxygen vacancy mechanism; (3) the dipole formation at the interface between high-k dielectric and interfacial SiO₂. The rest of dissertation focuses on the mechanism of Vfb shift by capping a thin layer of Me₂O₃ (Me=Gd, Y and Dy) on SiO₂ and HfO₂-based high-k dielectrics with TaN, W and Pt metal gate. It is proposed that the negative Vfb shift with TaN metal gate be due to the dipole formation at the interface between Me₂O₃ and the interfacial SiO₂. An XPS (X-ray photoelectron spectroscopy) study of Gd₂O₃ capping on SiO₂ indicates clear Si, O and Gd related bonding state change at the interface between Gd₂O₃ (or GdSiO) and the interfacial SiO₂. So the bonding state change is the root cause of the dipole formation. When there is an oxygen deficiency in Me₂O₃, another dipole formation through oxygen vacancy mechanism can also be observed. For a full understanding of the Vfb shift, all three FLP mechanisms must be considered. / text

The performance scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over four decades. Addressing the current challenges with CMOS scaling, the 2005 edition of International Technology Roadmap for Semiconductors has predicted the need for so-called technology boosters involving new materials for the gate dielectric and the channel as well as innovative structures. Theoretical studies suggest that the incorporation of high-mobility channel materials such as germanium and III-Vs could outperform bulk Si technology in terms of switching characteristics. Hence, this has recently led to tremendous research activity to explore the prospects of III-V materials for CMOS applications. Nevertheless, technological challenges such as formation of highquality interface between gate dielectric and III-V channel have hindered the demonstration of enhancement-mode III-V MOSFETs. Hence, tremendous effort has been devoted to study the exact origin of Fermi level pinning at the oxide/III-V interface. On the other hand, the advent of high-k materials has opened up the possibility of exploring new channel materials, for which it is challenging to achieve high-quality interface analogous to that of SiO2 on Si. Lately, III-Vs have been extensively explored in order to find compatible gate dielectrics which can unpin the Fermi level at the interface. Amongst various schemes, atomic layer deposition of high-k dielectrics offers some unique advantages such as reduction of GaAs interfacial oxides upon high-k deposition through an appropriate choice of precursor chemistry. The chief focus of this dissertation is to develop a simple wet clean process prior to high-k deposition, suitable for III-V substrates. The impact of various chemical treatments of GaAs substrates on the properties of high-k/GaAs interface was studied through extensive material and electrical characterization methods. The suitability of the ALD-grown high-k gate dielectrics on GaAs for MOSFET fabrication was explored. Charge trapping was found to result in significant errors in mobility extraction in high-k GaAs interface, where the role of high-k is not well understood. Hence, pulsed I-V and QV measurements and galvanomagnetic effects were utilized in order to directly measure the inversion charge in the channel without being affected by the charge traps as much as possible. It was also found that the material studies on GaAs substrates can be readily extended to other III-V channels, such as InGaAs. / text

This document details experiments attempting to increase the performance of metal-oxide-semiconductor field-effect-transistors (MOSFETs) which are the mainstay of the semiconductor industry. Replacing the silicon channel with an ultra-thin epitaxial germanium layer grown selectively on a silicon (100) bulk wafer is examined in detail. The gate oxide chosen for the germanium devices is a high-k gate oxide, HfO2, and the gate electrode is a metal gate, tantalum-nitride. They demonstrate large improvements in drive current and mobility over identically processed silicon PMOSFETs. In addition to the planar germanium PMOSFETs, a process has been developed for 50nm and smaller germanium P-finFETs and N and P germanium tunnel-FETs. The patterning of sub-30nm wide and 230nm tall three dimensional fins has been done with electron beam lithography and dry plasma etching. The processes to deposit high-k gate oxide and metal gates on the sub-30nm wide fins have been developed. All that remains for the production of these devices is electron beam lithography with a maximum misalignment error of 40nm. / text

Compared with its inorganic counterpart, organic thin-film transistor (OTFT) has advantages such as low-temperature fabrication, adaptability to large-area flexible substrate, and low cost. However, they usually need high operating voltage and thus are not suitable for portable applications. Although reducing their gate–dielectric thickness can lower the operating voltage, it increases their gate leakage. A better way is making use of high-κ gate dielectric, which is the main theme of this research. Firstly, pentacene OTFTs with HfO2 gate dielectric nitrided in N2O or NH3 at 200 oC were studied. The NH3-annealed OTFT displayed higher carrier mobility, larger on/off current ratio, smaller sub-threshold swing and smaller Hooge?s parameter than the N2O-annealed device. All these advantages were attributed to more nitrogen incorporation at the dielectric surface by the NH3 annealing which provided stronger passivation of surface traps. The incorporation of lanthanum to hafnium oxide was demonstrated to realize enhanced interface in the pentacene OTFTs. Therefore, pentacene OTFTs with HfLaO gate dielectric annealed in N2, NH3, O2 or NO at 400 oC were investigated. Among the 4 devices, the NH3-annealed OTFT obtained the highest carrier mobility, smallest sub-threshold swing and smallest 1/f noise. All these should be attributed to the improved interface between the gate dielectric and the organic semiconductor associated with the passivation effects of the NH3 annealing on the dielectric surface. The processing temperature of OTFTs is a big concern because use of flexible or glass substrate is the trend in organic electronics. Therefore, the HfLaO gate dielectric was annealed in N2, NH3, or O2 at two different temperatures, 200 oC and 400 oC. For all the annealing gases, the OTFTs annealed at 400 oC achieved higher carrier mobility, which could be supported by SEM image that pentacene tended to form larger grains (thus less carrier scattering) on HfLaO annealed at 400 oC. Furthermore, the HfLaO film annealed at 400 oC achieved much smaller leakage because more thermal energy at higher annealing temperature could remove oxide defects more effectively. Fluorination of the HfLaO film (annealed in N2 or NH3 at 400 oC) in a plasma based on CHF3 and O2 was also proposed. For both annealing gases, the OTFT with a 100-s plasma treatment achieved higher carrier mobility and smaller 1/f noise than that without plasma treatment. All these improvements should be due to fluorine incorporation at the dielectric surface which passivated the traps there. By contrast, for longer time (300 s or 900 s) of plasma treatment, the performance of the OTFTs deteriorated due to damage of dielectric surface induced by excessive plasma treatment. Lastly, a comparative study was done on pentacene OTFTs with HfLaO or La2O3 as gate dielectric. For the same annealing gas (H2, N2, NH3, or O2 at 400 oC), the OTFT with La2O3 gate dielectric obtained lower carrier mobility, smaller on/off current ratio, and larger threshold voltage than that based on HfLaO. The worse performance of the OTFTs with La2O3 gate dielectric was due to the degradation of La2O3 film caused by moisture absorption. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design process. To this end, considerable effort must be put into all phases of the design cycle. Effective CAD tools are essential for the production of high-performance digital systems. This thesis describes a CAD tool called LOVERD, which consists of ATPG, fault simulation, design verification and diagnosis. It uses test patterns, developed to detect single stuck-at faults in the gate-level implementation, to compare the results of the functional level description and its gate-level implementation. Whenever an error is detected, the logic diagnosis tool can be used to provide useful information to designers. It is shown that certain types of design errors in combinational logic circuits can be detected and allocated by LOVERD efficiently.