A new heuristic method to improve the I/O pad assignment for the sea-of-gates placement algorithm "PROUD" is proposed. In PROUD, the preplaced I/O pads are used as the boundary conditions in solving sparse linear equations to obtain the optimal module placement. Due to the total wire length determined by the module positions is the strong function of the preplaced I/O pad positions, the optimization of the I/O pad circular order and their assignment to the physical locations on the chip are attempted in the thesis. The proposed I/O pad assignment program is used as a predecessor of PROUD. The results have revealed excellent improvement.

Thesis (Ph. D.)--University of Texas at Austin, 2003. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.

Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. Recent advances in the area of floating-gate transistors have led to an analog technology that is very small, accurately programmable, and extremely low in power consumption. By leveraging the advantages of floating-gate devices, a large-scale FPAA is designed that dramatically advances the current state of the art in terms of size, functionality, and flexibility. A large-scale FPAA is used as part of a mixed-signal prototyping platform to demonstrate the viability and benefits of cooperative analog/digital signal processing. This work serves as a roadmap for future FPAA research. While current FPAAs can be compared with the small, relatively limited, digital, programmable logic devices (PLDs) of the 1970s and 1980s, the floating-gate FPAAs introduced here are the first step in enabling FPAAs to support large-scale, full-system prototyping of analog designs similar to modern FPGAs.

In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.

A complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor could be implemented, was proposed. Following the new polarization-based representation, a new Orthoparallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output once in a truth table, was developed. This representation allows for the implementation of all basic 16 logic gates, including the NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented, which opens the door for reconfigurable optical processors and programmable optical logic gates. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. The Rail Road (RR) architecture for polarization optical processors (POP) is presented. All the control inputs are applied simultaneously, leading to a single time lag, which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step design algorithm is provided for the POP, and design reduction methodologies are discussed. The algorithm lends itself systematically to software programming and computer-assisted design. A completely passive optical switch was also proposed. The switch is used to design completely passive optical gates, including the NAND gate, with their operational speeds only bound by the input beams prorogation delay. The design is used to demonstrate various circuits including the RS latch. Experimental data is reported for the NAND and the Universal gate operating with different functionality. A minute error is recorded in different cases, which can be easily eliminated by a more dedicated manufacturing process. Finally, some field applications are discussed and a comparison between all proposed systems and the current semiconductor devices is conducted based on multiple factors, including, speed, lag, and heat generation.

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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.