Electromagnetic interference (EMI) is a major concern in inverter motor drive systems. The sources of EMI have been commonly identified as high switching dv/dt and di/dt rates interacting with inverter parasitic components. The reduction of parasitic components relies on highly integrated circuit layout and packaging. This is the way to deal with noise path. On the other hand, switching dv/dt and di/dt can be potentially reduced by soft-switching techniques; thus the intensity of noise source is reduced. In this paper, the relation between the dv/dt di/dt and the EMI generation are discussed. The EMI sources of a hard-switching single-phase PWM inverter are identified and measured with separation of common-mode and differential-mode noises. The noise reduction in an auxiliary resonant snubber inverter (RSI) is presented. The observation of voltage ringing and current ringing and the methods to suppress these ringing in the implementation of RSI are also discussed. The test condition and circuit layout are described as the basis of the study. And the experimental EMI spectra of both hard- and soft-switching inverter are compared. The effectiveness and limitation of the EMI reduction of the ZVT-RSI are also discussed and concluded. The control interface circuit and gate driver design are described in the appendix. The implementation of variable charging time control of the resonant inductor current is also explained in the appendix. / Master of Science

As power conversion technology is being integrated further into high-reliability environments such as aerospace and electric vehicle applications, a full analysis and understanding of the system's robustness under operating conditions inside and outside the safe-operating-area is necessary. The robustness of power semiconductor devices, a primary component of power converters, has been traditionally evaluated through qualification tests that were developed for legacy silicon (Si) technologies. However, new devices have been commercialized using wide bandgap (WBG) semiconductors including silicon carbide (SiC) and gallium nitride (GaN). These new devices promise enhanced capabilities (e.g., higher switching speed, smaller die size, lower junction capacitances, and higher thermal conductance) over legacy Si devices, thus making the traditional qualification experiments ineffective. This work begins by introducing a new methodology for evaluating the switching robustness of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under these conditions, SiC MOSFETs show degradation in merely tens of hours at 25si{textdegree}C and tens of minutes at 100si{textdegree}C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, detected by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. The GaN high-electron-mobility transistor (HEMT) is a newer WBG device that is being increasingly adopted at an unprecedented rate. Different from SiC MOSFETs, GaN HEMTs have no avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. As a result, the dynamic breakdown voltage (BV) and transient overvoltage margin of GaN devices must be studied to fully evaluate the switching ruggedness of devices. This work characterizes the transient overvoltage capability and failure mechanisms of GaN HEMTs under hard-switched turn-off conditions at increasing temperatures, by using a clamped inductive switching circuit with a variable parasitic inductance. This test method allows flexible control over both the magnitude and the dV/dt of the transient overvoltage. The overvoltage robustness of two commercial enhancement-mode (E-mode) p-gate HEMTs was extensively studied: a hybrid drain gate injection transistor (HD-GIT) with an Ohmic-type gate and a Schottky p-Gate HEMT (SP-HEMT). The overvoltage failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. The HD-GIT and the SP-HEMT were found to fail at a voltage overshoot magnitude that is higher than the breakdown voltage in the static current-voltage measurement. These single event failure tests were repeated at increasing temperatures (100si{textdegree}C and 150si{textdegree}C), and the failures of both devices were consistent with room temperature results. The two types of devices show different failure behaviors, and the underlying mechanisms (electron trapping) have been revealed by physics-based device simulations. Once this single-event overvoltage failure was established, the device's robustness under repetitive overvoltage and surge-energy events remained unclear; therefore, the switching robustness was evaluated for both the HD-GIT and SP-HEMT in a clamped, inductive switching circuit with a 400 V dc bias. A parasitic inductance was used to generate the overvoltage stress events with different overvoltage magnitude up to 95% of the device's destructive limit, different switching periods from 10 ms to 0.33 ms, different temperatures up to 150si{textdegree}C, and different negative gate biases. The electrical parameters of these devices were measured before and after 1 million stress cycles under varying conditions. The HD-GITs showed no failure or permanent degradation after 1-million overvoltage events at different switching periods, or elevated temperatures. The SP-HEMTs showed more pronounced parametric shifts after the 1 million cycles in the threshold voltage, on-resistance, and saturation drain current. Different shifts were also observed from stresses under different overvoltage magnitudes and are attributable to the trapping of the holes produced in impact ionization. All shifts were found to be recoverable after a relaxation period. Overall, the results from these switching-oriented robustness tests have shown that SiC MOSFETs show a tremendous lifetime under static dc-bias experiments, but when excited by hard-switching turn-off events, the failure mechanisms are accelerated. These results suggest the insufficient robustness of SiC MOSFETs under high bias, hard switching conditions, and the significance of using switching-based tests to evaluate the device robustness. These inspired the GaN-based hard-switching turn-off robustness experiments, which further demonstrated the dynamic breakdown voltage phenomena. Ultimately these results suggest that the breakdown voltage and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static breakdown voltage. Both sets of experiments provide further evidence for the need for switching-oriented robustness experiments to be implemented by both device vendors and users, to fully qualify and evaluate new power semiconductor transistors. / Doctor of Philosophy / Power conversion technology is being integrated into industrial and commercial applications with the increased use of laptops, server centers, electric vehicles, and solar and wind energy generation. Each of these converters requires the power semiconductor devices to convert energy reliably and safely. textcolor{black}{Silicon has been the primary material for these devices; however,} new devices have been commercialized from both silicon carbide (SiC) and gallium nitride (GaN) materials. Although these devices are required to undergo qualification testing, the standards were developed for silicon technology. The performance of these new devices offers many additional benefits such as physically smaller dimensions, greater power conversion efficiency, and higher thermal operating capabilities. To facilitate the increased integration of these devices into industrial applications, greater robustness and reliability analyses are required to supplement the traditional tests. The work presented here provides two new experimental methodologies to test the robustness of both SiC and GaN power transistors. These methodologies are oriented around hard-switching environments where both high voltage biases and high conduction current exist and stress the intrinsic semiconductor properties. Experimental evaluations were conducted of both material technologies where the electrical properties were monitored over time to identify any degradation effects. Additional analyses were conducted to determine the physics-oriented failure mechanisms. This work provides insight into the limitations of these semiconductor devices for both device designers and manufacturers as well as power electronic system designers.

This diploma thesis deals with design and comparison of selected DC/DC converters, where the better of them is practically realized. The first part of the diploma thesis is focused on the general analysis of DC/DC power converters. The following part is theoretical analysis focused on the first selected topology – step-up converter. The second analysed topology is forward converter with full bridge on the primary side. The theoretical analysis also includes a description of synchronous rectifier, the differences between hard and soft switching, and the types of secondary rectifiers. Another part specializes in the detailed calculation of main components of selected converters and their subsequent power dimensioning. Both designed topologies are compared according to the required aspects. The selected better topology is supplemented by the design of control circuits and an auxiliary power supply. Practical realization of converter and commissioning follows. The diploma thesis ends with verification measurements on the realized converter and their subsequent analysis.

Characterizing  power  switches  is  an  indispensable  step  when  designing  a  converter.  This  thesisinvestigates ways to achieve static and dynamic characterization of semiconductors for high power applications such as power grid or train traction. The static characterization has been tested with a Keysight B1506A device analyzer. The problems encountered have been analyzed and corrected.Then the design of a high current switching test bench for dynamic characterization is explained. The full-bridge  configuration  allows  controlled  and  spontaneous  commutations  so  the  bench  can measure hard and soft switching. The voltage can be up to 10 kV and the current up to 3 kA during the commutation. The choice of the probes is justified. The issues of bandwidth, input impedance and common mode current are taken into account. Data are processed in order to interpolate theswitching loss in hard and soft switching. / Karaktärisering  av  halvledarbrytare  är  ett  viktigt  steg  när  man  utformar  en  omvandlare.  Dennaavhandling undersöker olika sätt att uppnå statisk och dynamisk karakterisering av halvledare för högeffekttillämpningar såsom elnät eller ellok. Statisk karaktäriseringen har utförts med en Keysight B1506A-enhetsanalysator. De problem som uppstått har analyserats och korrigerats.Utformningen    av    en    testbänk    för    dynamisk    karakterisering    förklaras.    Den    kompletta bryggkonfigurationen möjliggör kontrollerad och spontan kommutation med spänningar upp till 10 kV och  strömmar  upp till 3 kA så att  bänken kan mäta hård  och mjuk  växling.  Valet  av sonderna förklaras.   Frågorna   om   bandbredd,   ingångsimpedans   och   common-mode   ström   tas   med   iberäkningen. Data bearbetas för att interpolera kopplings förlusten i hård och mjuk växling.