High-temperature integrated circuit (IC) design is one of the new frontiers in microelectronics that can significantly improve the performance of the electrical systems in extreme environment applications, including automotive, aerospace, well-logging, geothermal, and nuclear. Power modules (DC-DC converters, inverters, etc.) are key components in these electrical systems. Power-to-volume and power-to-weight ratios of these modules can be significantly improved by employing silicon carbide (SiC) based power switches which are capable of operating at much higher temperature than silicon (Si) and gallium arsenide (GaAs) based conventional devices. For successful realization of such high-temperature power electronic circuits, associated control electronics also need to perform at high temperature. In any power converter, gate driver circuit performs as the interface between a low-power microcontroller and the semiconductor power switches. This dissertation presents design, implementation, and measurement results of a silicon-on-insulator (SOI) based high-temperature (>200 _C) and high-voltage (>30 V) universal gate driver integrated circuit with high drive current (>3 A) for SiC power switches. This mixed signal IC has primarily been designed for automotive applications where the under-hood temperature can reach 200 _C. Prototype driver circuits have been designed and implemented in a Bipolar-CMOS- DMOS (BCD) on SOI process and have been successfully tested up to 200 _C ambient temperature driving SiC switches (MOSFET and JFET) without any heat sink and thermal management. This circuit can generate 30V peak-to-peak gate drive signal and can source and sink 3A peak drive current. Temperature compensating and temperature independent design techniques are employed to design the critical functional units like dead-time controller and level shifters in the driver circuit. Chip-level layout techniques are employed to enhance the reliability of the circuit at high temperature. High-temperature test boards have been developed to test the prototype ICs. An ultra low power on-chip temperature sensor circuit has also been designed and integrated into the gate-driver die to safeguard the driver circuit against excessive die temperature (_ 220 _C). This new temperature monitoring approach utilizes a reverse biased p-n junction diode as the temperature sensing element. Power consumption of this sensor circuit is less than 10 uW at 200 _C.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / In any electrical or electronic circuit, thermal energy is a quantity that is always present and generally must be considered in the specifications of any application. In many cases, the heat from the Joule effect, as well as from other internal and irreversible losses, represent the biggest share of maximum heat that a system can dissipate under normal operation. In Power Electronics, the study and application of semiconductor power switches are particularly important. Many solutions have been developed over the years aiming to mitigate electrical losses and heat built-up in semiconductor power switches. It is important to state that the current amount of research available to academics and the general public into thermal effects on semiconductor power switches is not as wide as that concerning the applications of those switches. It is remarkably reduced the amount of work concerning active cooling of semiconductor power switches and components, as well as concerning the behavior of semiconductor power switches and components under active cooling. Thus, there is a lack of studies aiming the investigation of the behavior of electric switches under different thermal loads. Because of this lack, this work is focused on a proposal of an equipment actively cools semiconductor power switches used in Power Electronics, particularly those usually found in switched mode power supplies. The main purpose of this work is to develop an equipment for being used on a lab bench based on Peltier technology that sets thermal action on semiconductor power switches, making possible the evaluation of the behavior of these switches under different thermal exposures and temperatures. Fist, the Peltier technology was investigated and, later on, a solution was developed allowing the usage of this technology on semiconductor power switches. A detailed description and the calculations of the developed thermoelectric system are presented. The results of this work are presented as a comparative study of the behavior and limits of performance of MOSFETs in DC-DC Boost converters under active cooling compared to traditional passive heat sinks. During active cooling the MOSFET was cooled below ambient temperature, assuring its external thermal safety. The experimental results confirm the operation as intended. The main confirmed advantages were greater dissipated power, increase of thermal margin and capacity of actively transferring heat to an overloaded area to another place. / Em qualquer circuito elétrico ou eletrônico, a energia térmica é uma grandeza que está sempre presente e em geral deve ser levada em conta nas especificações de qualquer aplicação. Em vários casos, o calor decorrente do efeito joule, bem como de outras perdas internas e irreversíveis, representam a parcela mais impactante da quantidade de calor limítrofe que um sistema consegue dissipar em operação normal. São de particular importância em Eletrônica de Potência o estudo e a aplicação de chaves semicondutoras. Várias soluções têm sido desenvolvidas ao longo dos anos no sentido de mitigar as perdas elétricas em chaves semicondutoras, bem como o aumento de temperatura nas mesmas durante operação. É importante frisar que atualmente a quantidade de pesquisas disponíveis ao público acadêmico e geral sobre os efeitos térmicos em chaves semicondutoras não é tão ampla quanto sobre as aplicações dessas chaves. É particularmente reduzida a quantidade de trabalhos ligados ao resfriamento ativo de chaves e componentes elétricos, assim como de trabalhos voltados ao comportamento de chaves e componentes mediante resfriamento ativo. Sendo assim, existe uma carência de estudos que objetivem a investigação do comportamento de chaves semicondutoras mediante distintas cargas térmicas. Diante desta carência, o foco deste trabalho é apresentar uma proposta de equipamento que atue termicamente, seja aquecendo ou resfriando, sobre chaves semicondutoras utilizadas em eletrônica de potência, particularmente aquelas comumente usadas em fontes elétricas chaveadas. O objetivo principal deste trabalho é desenvolver um equipamento para uso em bancada baseado na tecnologia Peltier que resfrie ativamente chaves semicondutoras, possibilitando a avaliação de comportamento das mesmas mediante diferente exposições térmicas e temperaturas. Primeiramente a tecnologia Peltier foi investigada e, posteriormente, foi desenvolvida uma solução que permite a utilização desta tecnologia em dispositivos semicondutores de distintos encapsulamentos. Uma descrição detalhada e os cálculos de dimensionamento do sistema termoelétrico desenvolvido são apresentados. Os resultados deste trabalho são apresentados em forma de estudo comparativo sobre o comportamento e limites de desempenho de MOSFETs em conversores CC-CC Boost mediante resfriamento ativo frente aos tradicionais dissipadores passivos. Durante resfriamento ativo o MOSFET foi resfriado à temperatura subambiente e constante, garantindo sua a segurança térmica relacionada à temperatura do encapsulamento. Os resultados experimentais confirmam a operação do protótipo conforme a proposta deste trabalho. As principais vantagens confirmadas foram maior potência dissipada, aumento da margem térmica e capacidade de transferir ativamente calor de uma área sobrecarregada para outro local. / Mestre em Ciências

Ce travail porte sur l'étude du mélange thermodurcissable - thermoplastique (époxyamine / polyetherimide avec séparation de phase) pour évaluer les performances électriques et thermiques. Ces matériaux seraient des nouveaux candidats pour remplacer la couche d'encapsulation dans les semi-conducteurs, par exemple ceux utilisés comme interrupteur dans les applications électroniques de puissance. Les mélanges de polymères seraient un nouveau candidat en tant qu'isolant pour le système. La matrice epoxy-amine seul et les melanges epoxy / Polyetherimide on été caractérisés par microscopie électronique à transmission, microscopie électronique à balayage, Calorimétrie différentielle à balayage, analyse thermogravimétrique, analyse mécanique dynamique, analyse diélectrique avec simulation analytique et des mesures de conductivité électrique et de tension de claquage ont également été entreprises. Ces techniques complémentaires ont d'abord été utilisées pour étudier la séparation de phases et ensuite pour quantifier la taille des nodules de thermoplastiques dans la matrice thermodurcissable. Cette séparation de phase a été examiné et a montré une diminution des valeurs diélectriques de 15% et une augmentation de la tension de claquage par rapport au système époxy-amine pur. / This work deals with the study of thermoset-thermoplastic blend (epoxy-amine/poly-etherimide phase separated) to assess the electrical and thermal performances. These materials would be new candidates to replace the encapsulation layer in semiconductors, for example ones used as switches in power electronic applications. Polymers blends would be a novel candidate as an insulator for the system. Pure epoxy system as well as Epoxy/Polyetherimide blends where characterized by transmission electron microscopy, scanning electron microscopy, differential scanning calorimetry, thermogravimetric analysis, dynamic mechanical analysis, dielectric analysis with analytical simulation, electrical conductivity and breakdown voltage measurements. These complementary techniques were used first to investigate the presence of the phase separation phenomenon and secondly to quantify the separated nodules size. The effect of this phase separation was examined and showed a decrease in the dielectric values of 15 % and an increase in the breakdown voltage compared to the pure epoxy system. It was finally simulated to show a close assumption of what is found experimentally.

Characterizing  power  switches  is  an  indispensable  step  when  designing  a  converter.  This  thesisinvestigates ways to achieve static and dynamic characterization of semiconductors for high power applications such as power grid or train traction. The static characterization has been tested with a Keysight B1506A device analyzer. The problems encountered have been analyzed and corrected.Then the design of a high current switching test bench for dynamic characterization is explained. The full-bridge  configuration  allows  controlled  and  spontaneous  commutations  so  the  bench  can measure hard and soft switching. The voltage can be up to 10 kV and the current up to 3 kA during the commutation. The choice of the probes is justified. The issues of bandwidth, input impedance and common mode current are taken into account. Data are processed in order to interpolate theswitching loss in hard and soft switching. / Karaktärisering  av  halvledarbrytare  är  ett  viktigt  steg  när  man  utformar  en  omvandlare.  Dennaavhandling undersöker olika sätt att uppnå statisk och dynamisk karakterisering av halvledare för högeffekttillämpningar såsom elnät eller ellok. Statisk karaktäriseringen har utförts med en Keysight B1506A-enhetsanalysator. De problem som uppstått har analyserats och korrigerats.Utformningen    av    en    testbänk    för    dynamisk    karakterisering    förklaras.    Den    kompletta bryggkonfigurationen möjliggör kontrollerad och spontan kommutation med spänningar upp till 10 kV och  strömmar  upp till 3 kA så att  bänken kan mäta hård  och mjuk  växling.  Valet  av sonderna förklaras.   Frågorna   om   bandbredd,   ingångsimpedans   och   common-mode   ström   tas   med   iberäkningen. Data bearbetas för att interpolera kopplings förlusten i hård och mjuk växling.

Ce manuscrit est une contribution à l’étude de la fiabilité et de la robustesse des composants MOSFET sur carbure de silicium, matériau semi-conducteur grand gap qui possède des caractéristiques bien meilleures que le silicium. Ces nouveaux interrupteurs de puissances permettent d’obtenir entre autres propriétés remarquables, des fréquences de commutations et des tenues en tension plus élevées dans les systèmes de conversions de puissance. Ils sont particulièrement mis en avant depuis un peu plus d’une dizaine d’années pour les gains en performances, diminution des tailles et poids qu’ils apportent à certaines topologies de convertisseurs pour les réseaux haute tension à courant continu. Puis sont répertoriés les principaux mécanismes de défaillances de ces MOSFET SiC induits par la faiblesse de la grille. Toutes les mesures nécessaires au suivi des paramètres clés lors des prochains vieillissements sont présentées. Les résultats de nos tests sur l’instabilité de la tension de seuil sont aussi détaillés et un modèle empirique pour valider le comportement de relaxation observé est proposé. Celui-ci nous aidera par la suite à établir un protocole de mesure rigoureux de la tension de seuil. Les tests expérimentaux et résultats de vieillissement en statique et dynamique sur les composants 1,7 kV vont permettre de se rendre compte de l’importance de la dérive de la tension de seuil sur 1000 h. Dans le cas d’un vieillissement statique, il y a environ 7 % de dérive positive du VTH et un pourcentage équivalent pour les tests dynamiques. Des analyses supplémentaires (C-V et pompage de charge) sur l’oxyde de grille en cours de vieillissement sont proposées pour une meilleure compréhension des mécanismes mis en jeu dans la dégradation de l’oxyde. Enfin, les derniers tests présentés seront focalisés sur le comportement en court-circuit et courts-circuits répétitifs des mêmes composants. Avec une énergie critique évaluée autour de 1,5 J nos tests sur les MOSFET 1,7 kV montrent les limites de la robustesse de ces composants, avec une tenue en court-circuit bien inférieure à 10 µs et une incapacité à résister à plus de 150 courts-circuits successifs. L’influence de la tension entre drain et source y est notamment étudiée, et montre que l’énergie critique supportée par le composant diminue avec l’augmentation de cette tension. / This manuscript is a contribution to reliability and robustness study of MOSFET components on silicon carbide “SiC”, wide band gap semiconductor with better characteristics compared to silicon “Si” material. Those new power switches can provide better switching frequencies or voltage withstanding for example in power converter. SiC MOSFET are the results of approximately 10 years of research and development and can provide increased performances and weight to some converter topology for high voltage direct current networks. Others power switches available are still introduced and an introduction to reliability is explaining why such work on this new power switches is important. Transition from Si technologies to SiC ones require a lot of work regarding its robustness. Before showing reliability and robustness results is presented I give a lot of details regarding to the measurement and monitoring of key parameters used in the next chapters. The results of our tests on the threshold voltage instability are presented and how we validated an empirical model on this drift. This was used to propose an enhanced measurement protocol on the threshold voltage. Static and dynamic experimental results presented next will show if the voltage drift during ageing is significant or not. Further analysis is proposed to add more insight on the understanding of the oxide degradation mechanisms through C-V and charge pumping measurements. Finally, the ageing results presented on 1,7 kV SiC MOSFET are focused on the short-circuit and repetitive short-circuit behavior of the same components. Drain to source voltage influence on critical energy during this particular and stressful operation mode is studied. This time, the results are worrying.The last chapter is confidential.

La thèse intitulée "Conception, caractérisation et optimisation d’un transistor à effet de champ haute tension en Carbure de Silicium (SiC) et de leur diode associée", s’est déroulée au sein du laboratoire AMPERE sous la direction du Prof. D. PLANSON. Des premiers démonstrateurs de JFET ont été réalisés. Le blocage du JFET n'est pas efficace, ceci étant lié aux difficultés de réalisation technologique. Le premier travail a consisté en leur caractérisation précise puis en leur simulation, en tenant compte des erreurs de processus de fabrication. Ensuite, un nouveau masque a été dessiné en tenant en compte des problèmes technologiques identifiés. Les performances électriques de la nouvelle génération du composant ont ainsi démontré une amélioration importante au niveau de la tenue en tension. Dans le même temps, de nouveaux problèmes se sont révélés, qu’il sera nécessaire de résoudre dans le cadre de travaux futurs. Par ailleurs, les aspects de tenue en court-circuit des JFETs en SiC commercialement disponibles ont été étudiés finement. Les simulations électrothermiques par TCAD ont révélé les modes de défaillances. Ceci a permis d'établir finalement des modèles physiques valables pour les JFETs en SiC. / Silicon carbide (SiC) has higher critical electric field for breakdown and lower intrinsic carrier concentration than silicon, which are very attractive for high power and high temperature power electric applications. In this thesis, a new 3.3kV/20A SiC-4H JFET is designed and fabricated for motor drive (330kW). This breakdown voltage is beyond the state of art of the commercial unipolar SiC devices. The first characterization shows that the breakdown voltage is lower (2.5kV) than its theoretical value. Also the on-state resistance is more important than expected. By means of finite element simulation the origins of the failure are identified and then verified by optical analysis. Hence, a new layout is designed followed by a new generation of SiC-4H JFET is fabricated. Test results show the 3.3kV JFET is developed successfully. Meanwhile, the electro-thermal mechanism in the SiC JFETs under short circuit is studied by means of TCAD simulation. The commercial 1200V SIT (USCi) and LV-JFET (Infineon) are used as sample. A hotspot inside the structures is observed. And the impact the bulk thickness and the canal doping on the short circuit capability of the devices are shown. The physical models validated by this study will be used on our 3.3kV once it is packaged.