abstract: Electrical neural activity detection and tracking have many applications in medical research and brain computer interface technologies. In this thesis, we focus on the development of advanced signal processing algorithms to track neural activity and on the mapping of these algorithms onto hardware to enable real-time tracking. At the heart of these algorithms is particle filtering (PF), a sequential Monte Carlo technique used to estimate the unknown parameters of dynamic systems. First, we analyze the bottlenecks in existing PF algorithms, and we propose a new parallel PF (PPF) algorithm based on the independent Metropolis-Hastings (IMH) algorithm. We show that the proposed PPF-IMH algorithm improves the root mean-squared error (RMSE) estimation performance, and we demonstrate that a parallel implementation of the algorithm results in significant reduction in inter-processor communication. We apply our implementation on a Xilinx Virtex-5 field programmable gate array (FPGA) platform to demonstrate that, for a one-dimensional problem, the PPF-IMH architecture with four processing elements and 1,000 particles can process input samples at 170 kHz by using less than 5% FPGA resources. We also apply the proposed PPF-IMH to waveform-agile sensing to achieve real-time tracking of dynamic targets with high RMSE tracking performance. We next integrate the PPF-IMH algorithm to track the dynamic parameters in neural sensing when the number of neural dipole sources is known. We analyze the computational complexity of a PF based method and propose the use of multiple particle filtering (MPF) to reduce the complexity. We demonstrate the improved performance of MPF using numerical simulations with both synthetic and real data. We also propose an FPGA implementation of the MPF algorithm and show that the implementation supports real-time tracking. For the more realistic scenario of automatically estimating an unknown number of time-varying neural dipole sources, we propose a new approach based on the probability hypothesis density filtering (PHDF) algorithm. The PHDF is implemented using particle filtering (PF-PHDF), and it is applied in a closed-loop to first estimate the number of dipole sources and then their corresponding amplitude, location and orientation parameters. We demonstrate the improved tracking performance of the proposed PF-PHDF algorithm and map it onto a Xilinx Virtex-5 FPGA platform to show its real-time implementation potential. Finally, we propose the use of sensor scheduling and compressive sensing techniques to reduce the number of active sensors, and thus overall power consumption, of electroencephalography (EEG) systems. We propose an efficient sensor scheduling algorithm which adaptively configures EEG sensors at each measurement time interval to reduce the number of sensors needed for accurate tracking. We combine the sensor scheduling method with PF-PHDF and implement the system on an FPGA platform to achieve real-time tracking. We also investigate the sparsity of EEG signals and integrate compressive sensing with PF to estimate neural activity. Simulation results show that both sensor scheduling and compressive sensing based methods achieve comparable tracking performance with significantly reduced number of sensors. / Dissertation/Thesis / Ph.D. Electrical Engineering 2013

No description available.

The Atomic Force Microscope (AFM) is a powerful tool for studying structure and dynamics at the nanometer scale. Despite its wide application in many applications, the slow imaging rate of AFM remains a severe limitation. Non-raster methods seek to overcome this limitation by appealing to alternative scan patterns, either designed to be easier for the actuators to follow or to reduce the amount of sampling needed. One particular example in this latter category is the local circular scan (LCS). LCS reduces the imaging time by scanning less sample area rather than scanning faster. It drives the tip of the AFM along a circular trajectory, using feedback to center that circle on a sample edge, and moving the circle along the feature, thus concentrating the samples to the region of interest. While this approach can have a significant impact on improving the imaging rate of any AFM, its impact is further enhanced when it is combined with high speed scanners. Due to its unique scanning pattern, a high-speed, Dual-Stage Actuator (DSA) system is a natural fit. DSAs consist of the serial combination of a (relatively) low-speed, long-range piezoelectric actuator (LRA) and a high-speed, short-range piezoelectric actuator (SRA). The SRA can be dedicated to implementing the local circular motion and the LRA to tracking the underlying sample. However, the control of a DSA scanner is challenging for at least three reasons: it is a multi-input, single-output system, it is a highly resonant system due to the underlying piezoelectric actuators, and it is a high-speed system. In this thesis, we address these challenges. First, we establish the controllability and observability of a general N-stage system whose outputs are summed to produce a single signal. This property allows us to develop individual controllers for the LRA and SRA of a DSA system so that we can focus our design on the specific requirements of each component and its desired action. While we apply both a Model Predictive Control (MPC) and simple state feedback approach to the LRA, our primary focus is on the SRA element as its high speed character makes it the more challenging component. Here we turn to receding horizon Linear Quadratic Tracking (LQT) control and develop methods to implement this approach at high speed using a Field Programmable Gate Array (FPGA). We develop three variants of LQT that differ in the required sample rates, memory resources, and computing power. Implementing and testing all three in both simulation and on a DSA scanning stage in our lab, we compare their performance and address the practical implementation considerations under the limitations imposed by the hardware. Finally, we combine the control of the LRA and SRA in two axes to demonstrate the LCS scanning approach. Overall, this thesis achieves a practical implementation of a model-based receding LQT design on a dual-stage, high speed, highly resonant actuator system. Through both simulation and experimental results, we demonstrate that this approach is robust to modeling error and disturbances and suitable for high-speed implementation of the LCS approach to non-raster AFM. / 2023-08-29T00:00:00Z

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No description available.

No description available.

Neste trabalho apresenta-se uma proposta de uma técnica para implementação em hardware, das estruturas básicas de uma Rede Neural Competitiva, baseada em técnicas analógicas. Através desta proposta, será abordada uma das classes mais interessantes de Redes Neurais Artificiais (RNA) que são as Redes Neurais Competitivas (RNC), que possuem forte inspiração biológica. As equações fundamentais que descrevem o comportamento da RNC foram derivadas de estudos interdisciplinares, a maioria envolvendo observações neurofisiológicas. O estudo do neurônio biológico, por exemplo, nos leva a clássica equação da membrana. A técnica mostrada para a implementação das Redes Neurais Competitivas se baseia no use das técnicas analógicas. Estas conduzem a um projeto mais compacto além de permitirem um processamento em tempo real, visto que o circuito computacional analógico altera simultaneamente e continuamente todos os estados dos neurônios que se encontram interligados em paralelo. Para esta proposta de implementação, a mostrado que as equações fundamentais que governam as Redes Neurais Competitivas possuem uma relação com componentes eletrônicos básicos, podendo então, serem implementados através destes simples componentes com os quais as equações fundamentais se relacionam. Para tanto, é mostrado por meio de simulações em software, o comportamento das equações fundamentais deste tipo de Redes Neurais, e então, é comparado este comportamento, com os obtidos através de simulações elétricas dos circuitos equivalentes oriundos destas equações fundamentais. Mostra-se também, em ambas as simulações, uma das características mais importantes existentes nos modelos de RNC, conhecida como Memória de Tempo Curto (STM). Por fim, é apresentada uma aplicação típica na área de clusterização de padrões utilizando pesos sinápticos, a fim de demonstrar a implementação utilizando as técnicas descritas durante o trabalho. Esta aplicação é demonstrada através de simulações elétricas, sendo estas realizadas para tipos diferentes de tecnologia, mostrando assim, o correto desempenho da proposta deste trabalho. / In this work we present a proposal of a technique to hardware implementation of the basic structures of a Competitive Neural Network, based on analog circuits techniques. This proposal approaches one of the most interesting classes of Artificial Neural Networks (ANN) that are the Competitive Neural Networks (CNN), that possess strong biological inspiration. The fundamental equations that describe the behavior of CNN were derived from interdisciplinary studies, mostly involving neurophysiological observations. The study of the biological neuron, for example, leads to the classical membrane equation. The presented technique for implementation of Competitive Neural Networks is based on the use of analog circuits techniques. This leads to a more compact project and allows real time processing, because computation in analog circuits modifies simultaneously and continuouslly all the states of the neurons that are connected in parallel. In this proposal, it is shown that the fundamental equations that describe the behavior of Competitive Neural Networks possess a relationship with some basic electronic components. This fact allows the direct implementation of CNN with these electronic components. Initially the behavior of the fundamental equations of this type of Neural Networks is studied by means of software simulations. This behavior is then compared, with the one obtained through electric simulations of the equivalent circuits originated from these fundamental equations. It is also shown, in both simulations, one of the more important characteristic in the models of CNN, known as Short Term Memory (STM). Finally, a typical application is presented in the area of pattern clustering using synaptic weights, to demonstrate an implementation using the techniques described in this work. This application is demonstrated through electric simulations, for different IC technologies, comproving the correctness of the presented proposal.

Neste trabalho apresenta-se uma proposta de uma técnica para implementação em hardware, das estruturas básicas de uma Rede Neural Competitiva, baseada em técnicas analógicas. Através desta proposta, será abordada uma das classes mais interessantes de Redes Neurais Artificiais (RNA) que são as Redes Neurais Competitivas (RNC), que possuem forte inspiração biológica. As equações fundamentais que descrevem o comportamento da RNC foram derivadas de estudos interdisciplinares, a maioria envolvendo observações neurofisiológicas. O estudo do neurônio biológico, por exemplo, nos leva a clássica equação da membrana. A técnica mostrada para a implementação das Redes Neurais Competitivas se baseia no use das técnicas analógicas. Estas conduzem a um projeto mais compacto além de permitirem um processamento em tempo real, visto que o circuito computacional analógico altera simultaneamente e continuamente todos os estados dos neurônios que se encontram interligados em paralelo. Para esta proposta de implementação, a mostrado que as equações fundamentais que governam as Redes Neurais Competitivas possuem uma relação com componentes eletrônicos básicos, podendo então, serem implementados através destes simples componentes com os quais as equações fundamentais se relacionam. Para tanto, é mostrado por meio de simulações em software, o comportamento das equações fundamentais deste tipo de Redes Neurais, e então, é comparado este comportamento, com os obtidos através de simulações elétricas dos circuitos equivalentes oriundos destas equações fundamentais. Mostra-se também, em ambas as simulações, uma das características mais importantes existentes nos modelos de RNC, conhecida como Memória de Tempo Curto (STM). Por fim, é apresentada uma aplicação típica na área de clusterização de padrões utilizando pesos sinápticos, a fim de demonstrar a implementação utilizando as técnicas descritas durante o trabalho. Esta aplicação é demonstrada através de simulações elétricas, sendo estas realizadas para tipos diferentes de tecnologia, mostrando assim, o correto desempenho da proposta deste trabalho. / In this work we present a proposal of a technique to hardware implementation of the basic structures of a Competitive Neural Network, based on analog circuits techniques. This proposal approaches one of the most interesting classes of Artificial Neural Networks (ANN) that are the Competitive Neural Networks (CNN), that possess strong biological inspiration. The fundamental equations that describe the behavior of CNN were derived from interdisciplinary studies, mostly involving neurophysiological observations. The study of the biological neuron, for example, leads to the classical membrane equation. The presented technique for implementation of Competitive Neural Networks is based on the use of analog circuits techniques. This leads to a more compact project and allows real time processing, because computation in analog circuits modifies simultaneously and continuouslly all the states of the neurons that are connected in parallel. In this proposal, it is shown that the fundamental equations that describe the behavior of Competitive Neural Networks possess a relationship with some basic electronic components. This fact allows the direct implementation of CNN with these electronic components. Initially the behavior of the fundamental equations of this type of Neural Networks is studied by means of software simulations. This behavior is then compared, with the one obtained through electric simulations of the equivalent circuits originated from these fundamental equations. It is also shown, in both simulations, one of the more important characteristic in the models of CNN, known as Short Term Memory (STM). Finally, a typical application is presented in the area of pattern clustering using synaptic weights, to demonstrate an implementation using the techniques described in this work. This application is demonstrated through electric simulations, for different IC technologies, comproving the correctness of the presented proposal.

Neste trabalho apresenta-se uma proposta de uma técnica para implementação em hardware, das estruturas básicas de uma Rede Neural Competitiva, baseada em técnicas analógicas. Através desta proposta, será abordada uma das classes mais interessantes de Redes Neurais Artificiais (RNA) que são as Redes Neurais Competitivas (RNC), que possuem forte inspiração biológica. As equações fundamentais que descrevem o comportamento da RNC foram derivadas de estudos interdisciplinares, a maioria envolvendo observações neurofisiológicas. O estudo do neurônio biológico, por exemplo, nos leva a clássica equação da membrana. A técnica mostrada para a implementação das Redes Neurais Competitivas se baseia no use das técnicas analógicas. Estas conduzem a um projeto mais compacto além de permitirem um processamento em tempo real, visto que o circuito computacional analógico altera simultaneamente e continuamente todos os estados dos neurônios que se encontram interligados em paralelo. Para esta proposta de implementação, a mostrado que as equações fundamentais que governam as Redes Neurais Competitivas possuem uma relação com componentes eletrônicos básicos, podendo então, serem implementados através destes simples componentes com os quais as equações fundamentais se relacionam. Para tanto, é mostrado por meio de simulações em software, o comportamento das equações fundamentais deste tipo de Redes Neurais, e então, é comparado este comportamento, com os obtidos através de simulações elétricas dos circuitos equivalentes oriundos destas equações fundamentais. Mostra-se também, em ambas as simulações, uma das características mais importantes existentes nos modelos de RNC, conhecida como Memória de Tempo Curto (STM). Por fim, é apresentada uma aplicação típica na área de clusterização de padrões utilizando pesos sinápticos, a fim de demonstrar a implementação utilizando as técnicas descritas durante o trabalho. Esta aplicação é demonstrada através de simulações elétricas, sendo estas realizadas para tipos diferentes de tecnologia, mostrando assim, o correto desempenho da proposta deste trabalho. / In this work we present a proposal of a technique to hardware implementation of the basic structures of a Competitive Neural Network, based on analog circuits techniques. This proposal approaches one of the most interesting classes of Artificial Neural Networks (ANN) that are the Competitive Neural Networks (CNN), that possess strong biological inspiration. The fundamental equations that describe the behavior of CNN were derived from interdisciplinary studies, mostly involving neurophysiological observations. The study of the biological neuron, for example, leads to the classical membrane equation. The presented technique for implementation of Competitive Neural Networks is based on the use of analog circuits techniques. This leads to a more compact project and allows real time processing, because computation in analog circuits modifies simultaneously and continuouslly all the states of the neurons that are connected in parallel. In this proposal, it is shown that the fundamental equations that describe the behavior of Competitive Neural Networks possess a relationship with some basic electronic components. This fact allows the direct implementation of CNN with these electronic components. Initially the behavior of the fundamental equations of this type of Neural Networks is studied by means of software simulations. This behavior is then compared, with the one obtained through electric simulations of the equivalent circuits originated from these fundamental equations. It is also shown, in both simulations, one of the more important characteristic in the models of CNN, known as Short Term Memory (STM). Finally, a typical application is presented in the area of pattern clustering using synaptic weights, to demonstrate an implementation using the techniques described in this work. This application is demonstrated through electric simulations, for different IC technologies, comproving the correctness of the presented proposal.

Indiana University-Purdue University Indianapolis (IUPUI) / In this thesis, 3D image segmentation is targeted to a Xilinx Field Programmable Gate Array (FPGA), and verified with extensive simulation. Segmentation is performed using the Expectation-Maximization with Maximization of the Posterior Marginals (EM/MPM) Bayesian algorithm. This algorithm segments the 3D image using neighboring pixels based on a Markov Random Field (MRF) model. This iterative algorithm is designed, synthesized and simulated for the Xilinx FPGA, and greater than 100 times speed improvement over standard desktop computer hardware is achieved. Three new techniques were the key to achieving this speed: Pipelined computational cores, sixteen parallel data paths and a novel memory interface for maximizing the external memory bandwidth. Seven MPM segmentation iterations are matched to the external memory bandwidth required of a single source file read, and a single segmented file write, plus a small amount of latency.