This PhD thesis focuses on the study, the hardware design, the theoretical and practical validation, and eventually the comparison of different arithmetic operators for cryptosystems based on elliptic curves (ECC). Provided solutions must be robust against some side-channel attacks, and efficient at a hardware level (execution speed and area). In the case of ECC, we want to protect the secret key, a large integer, used in the scalar multiplication. Our protection methods use representations of numbers, and behaviour of algorithms to make more difficult some attacks. For instance, we randomly change some representations of manipulated numbers while ensuring that computed values are correct. Redundant representations like signed-digit representation, the double- (DBNS) and multi-base number system (MBNS) have been studied. A proposed method provides an on-the-fly MBNS recoding which operates in parallel to curve-level operations and at very high speed. All recoding techniques have been theoretically validated, simulated extensively in software, and finally implemented in hardware (FPGA and ASIC). A side-channel attack called template attack is also carried out to evaluate the robustness of a cryptosystem using a redundant number representation. Eventually, a study is conducted at the hardware level to provide an ECC cryptosystem with a regular behaviour of computed operations during the scalar multiplication so as to protect against some side-channel attacks.

At present, one of the main issues in electric power networks is the reduction in conventional generation and its replacement by low inertia renewable energy generation. The balance between generation and demand has a direct impact on the system frequency and system inertia limits the frequency rate of change until compensation action can be undertaken. Traditionally generation managed frequency. In future, loads may be required to do more than just be able to be switched off during severe under frequency events. This thesis focuses on the development and practical implementation of the control structure of a smart adaptive load for network power-frequency support applications. The control structure developed makes use of advanced demand side management of fan loads (powered by AC drives) used in heating, ventilation, and air conditioning systems; where a change in power at rated load has little effect on their speed due to the cubic relationship between speed and power. The AC drive implemented in this thesis is based on an induction motor and a two level voltage source converter. To achieve the smart adaptive load functionality, first a power-frequency multi-slope droop control structure (feedforward control) is developed; relating the frequency limits imposed by the network supplier and the fan power-speed profile (Chapter 2, Fig 2.19). Secondly, this control structure is combined with the control developed, in Chapter 3, for the AC drive powering the fan load. The full development of the control structure of the AC drive, its tuning process and its practical implementation is given; an equation is developed to find suitable tuning parameters for the speed control of the nonlinear load (fan load), i.e. Eq. (3.59).The analysis and simulation results provided in Chapter 4 conclude that a fast control of the active power drawn by the AC drive is possible by controlling the electromagnetic torque (hence current) of the induction motor without disturbing the fan load overly. To achieve this, changes between closed loop speed control and open loop torque control (power control) are performed when needed. Two main issues were addressed before the hardware implementation of the smart adaptive load: the estimation of the network frequency under distorted voltage conditions, and the recovery period of the network frequency. In this thesis two slew rate limiters were implemented to deal with such situations. Other possible solutions are also outlined. Finally, experimental results in Chapter 5 support results given in Chapter 4. A full power-frequency response is achieved by the smart adaptive load within 3s.

Le travail effectué dans cette thèse propose et évalue une solution au problème de coupure fréquente du courant électrique fourni par le réseau publique défaillant dans plusieurs pays en voie de développement. La solution consiste à installer un système de panneaux Photovoltaïques (PV) avec des batteries de stockage opérant conjointement avec le réseau. L’étude traite particu- lièrement le cas Libanais et considère une application résidentielle à consommation d’énergie élevée. La topologie du système proposé introduit des contraintes supplémentaires au fonction- nement de l’ensemble par rapport aux deux configurations classiques traitées dans la littérature, à savoir accrochage au réseau ou système autonome. L’étude vise principalement à maintenir une alimentation permanente en électricité du foyer ainsi qu’à réduire les frais du système installé tout en respectant les niveaux de confort exigés par les résidents. L’étude traite l’optimisation du système PV-Batteries, en partant du dimensionnement jusqu’au fonctionnement. Tout d’abord, sa configuration est optimisée en se basant sur une étude économique détaillée pour l’estimation des frais considérant une durée de vie de 20 ans. Le dimensionnement est formulé comme un problème d’optimisation visant la réduction du coût global du système. L’optimisation du fonctionnement du système PV-batterie vient en second lieu. Un algorithme de contrôle de charges est élaboré. Cet algorithme sert à éviter la coupure du courant électrique tout en mainte- nant des niveaux élevés de confort des habitants d’une part et en respectant les contraintes de fonctionnement du système d’autre part. La gestion des charges s’effectue à plusieurs niveaux, afin de gérer les charges prévisibles et imprévisibles. La commande développée assure la coordi- nation complète entre tous les composants de l’installation : réseau, panneaux PV, batteries de stockage et charges électriques. L’étude prouve que le contrôle des charges conçu ne se limite pas à l’optimisation du fonctionnement du système, mais contribue de même à la réduction de son coût global. Le logiciel établi est optimisé de sorte à assurer une faible consommation de mémoire et une prise de décision rapide afin de réaliser l’implémentation des codes sur des processeurs de type ARM Cortex-A9. Les résultats de simulation et d’implémentation montrent que le programme développé est générique, flexible, précis, rapide et fiable.Les résultats présentés dans cette thèse attestent que le système PV-batterie proposé est bien approprié pour remplacer le réseau public pendant les périodes de coupure du courant électrique dans une application résidentielle. De plus, ce système présente une bonne fiabilité surtout lorsqu’il est couplé avec le programme de contrôle des charges développé. / This thesis addresses the issue of intermittent primary energy source in several developing countries and considers, in particular, the case study of Lebanon. A PV-battery backup system is proposed and assessed as a replacement of the grid energy during daily power outage periods for a high energy consuming residential house. The proposed system topology introduces more critical conditions and additional constraints on the operation of the system compared to standard on-grid or standalone PV systems. The main concern is to provide permanent electricity supply to the house, reduce the resulting fees, and ensure high performance and reliability of the backup system while respecting the residents’ comfort levels. This thesis aims at thoroughly assessing the suitability of the proposed backup system by focusing on various aspects of the system. First, its configuration is optimized through the development of a detailed economic study estimating the resulting fees over its 20-year lifetime. The sizing process is formulated as an optimization problem having the sole objective of minimizing the overall cost of the system. Furthermore, a detailed comparative study of various water heating techniques is conducted to the end of determining the most suitable configuration to be coupled with the proposed backup solution. Second, the thesis targets the operation optimization of the PV-battery system by implementing a Demand Side Management (DSM) program aiming at preventing the occurrence of loss of power supply to the house while maintaining high comfort levels to the inhabitants and respecting the operation constraints of the system. The control is divided into several layers in order to manage predictable and unpredictable home appliances. The strength of the developed control lies in ensuring the complete coordination between all the components of the installation: the grid, PV panels, battery storage, and the load demand. The benefits of the DSM are proven to go beyond the operation optimization of the system since they highly affect the sizing of the backup, and by extension, the overall resulting cost. The established program is optimized for the hardware implementation process by ensuring a low memory consumption and fast decision making. The developed C codes of the full DSM program are implemented on ARM Cortex-A9 processors. The simulation and implementation results show that the developed management program is highly generic, flexible, accurate, fast, and reliable.The results presented in this thesis validate that the proposed PV-Battery backup system is highly suitable to assist unreliable grids. It outperforms currently installed Diesel Generators and demonstrates a remarkable reliability especially when coupled with the developed DSM program.

In this thesis, we have proposed a new computing platform called probabilistic spin logic (PSL) based on probabilistic bits (p-bit) using low barrier nanomagnets (LBM) whose thermal barrier is of the order of a kT unlike conventional memory and spin logic devices that rely on high thermal barrier magnets (40-60 kT) to retain stability. p-bits are tunable random number generators (TRNG) analogous to the concept of binary stochastic neurons (BSN) in artificial neural network (ANN) whose output fluctuates between a +1 and -1 states with 50-50 probability at zero input bias and the stochastic output can be tuned by an applied input producing a sigmoidal characteristic response. p-bits can be interconnected by a synapse or weight matrix [J] to build p-circuits for solving a wide variety of complex unconventional problems such as inference, invertible Boolean logic, sampling and optimization. It is important to update the p-bits sequentially for proper operation where each p-bit update is informed of the states of other p-bits that it is connected to and this requires the use of sequencers in digital clocked hardware. But the unique feature of our probabilistic hardware is that they are autonomous that runs without any clocks or sequencers.<br>To ensure the necessary sequential informed update in our autonomous hardware it is important that the synapse delay is much smaller than the neuron fluctuation time.<br>We have demonstrated the notion of this autonomous hardware by SPICE simulation of different designs of low barrier nanomagnet based p-circuits for both symmetrically connected Boltzmann networks and directed acyclic Bayesian networks. It is interesting to note that for Bayesian networks a specific parent to child update order is important and requires specific design rule in the autonomous probabilistic hardware to naturally ensure the specific update order without any clocks. To address the issue of scalability of these autonomous hardware we have also proposed and benchmarked compact models for two different hardware designs against SPICE simulation and have shown that the compact models faithfully mimic the dynamics of the real hardware.<br>

The thesis focuses on power analysis of modern cryptographic modules. The first part contains a brief introduction to the topic of the power side channel and basic methods of analyzes. The text describes the process of comparison of modules and a short description of devices found. In the practical part two modules has been selected for the implementation of the encryption algorithm AES-128. The first module was the chip card Gemalto .NET v2 and the second one was the Raspberry Pi. A workplace has been created for these modules which allowed to measure the power consumption of the algorithm AES. Differential Power Analysis has been made using the captured results. In its conclusion the work presents the results in tables and samples of source codes. Graphs were made from the results captured on the Raspberry Pi and from the results of the Differential Power Analysis.

Cette thèse porte sur l'étude, la conception matérielle, la validation théorique et pratique, et enfin la comparaison de différents opérateurs arithmétiques pour des cryptosystèmes basés sur les courbes elliptiques (ECC). Les solutions proposées doivent être robustes contre certaines attaques par canaux cachés tout en étant performantes en matériel, tant au niveau de la vitesse d'exécution que de la surface utilisée. Dans ECC, nous cherchons à protéger la clé secrète, un grand entier, utilisé lors de la multiplication scalaire. Pour nous protéger contre des attaques par observation, nous avons utilisé certaines représentations des nombres et des algorithmes de calcul pour rendre difficiles certaines attaques ; comme par exemple rendre aléatoires certaines représentations des nombres manipulés, en recodant certaines valeurs internes, tout en garantissant que les valeurs calculées soient correctes. Ainsi, l'utilisation de la représentation en chiffres signés, du système de base double (DBNS) et multiple (MBNS) ont été étudiés. Toutes les techniques de recodage ont été validées théoriquement, simulées intensivement en logiciel, et enfin implantées en matériel (FPGA et ASIC). Une attaque par canaux cachés de type template a de plus été réalisée pour évaluer la robustesse d'un cryptosystème utilisant certaines de nos solutions. Enfin, une étude au niveau matériel a été menée dans le but de fournir à un cryptosystème ECC un comportement régulier des opérations effectuées lors de la multiplication scalaire afin de se protéger contre certaines attaques par observation. / This PhD thesis focuses on the study, the hardware design, the theoretical and practical validation, and eventually the comparison of different arithmetic operators for cryptosystems based on elliptic curves (ECC). Provided solutions must be robust against some side-channel attacks, and efficient at a hardware level (execution speed and area). In the case of ECC, we want to protect the secret key, a large integer, used in the scalar multiplication. Our protection methods use representations of numbers, and behaviour of algorithms to make more difficult some attacks. For instance, we randomly change some representations of manipulated numbers while ensuring that computed values are correct. Redundant representations like signed-digit representation, the double- (DBNS) and multi-base number system (MBNS) have been studied. A proposed method provides an on-the-fly MBNS recoding which operates in parallel to curve-level operations and at very high speed. All recoding techniques have been theoretically validated, simulated extensively in software, and finally implemented in hardware (FPGA and ASIC). A side-channel attack called template attack is also carried out to evaluate the robustness of a cryptosystem using a redundant number representation. Eventually, a study is conducted at the hardware level to provide an ECC cryptosystem with a regular behaviour of computed operations during the scalar multiplication so as to protect against some side-channel attacks.

Spacecrafts are extensively used by public and private sectors to support a variety of services. Considering the cost and the strategic importance of these spacecrafts, there has been an increasing demand to utilize strong cryptographic primitives to assure their security. Moreover, it is of utmost importance to consider fault tolerance in their designs due to the harsh environment found in space, while keeping low area and power consumption. The problem of recovering spacecrafts from failures or attacks, and bringing them back to an operational and safe state is crucial for reliability. Despite the recent interest in incorporating on-board security, there is limited research in this area. This research proposes a trusted hardware module approach for recovering the spacecrafts subsystems and their cryptographic capabilities after an attack or a major failure has happened. The proposed fault tolerant trusted modules are capable of performing platform restoration as well as recovering the cryptographic capabilities of the spacecraft. This research also proposes efficient fault tolerant architectures for the secure hash (SHA-2) and message authentication code (HMAC) algorithms. The proposed architectures are the first in the literature to detect and correct errors by using Hamming codes to protect the main registers. Furthermore, a quantitative analysis of the probability of failure of the proposed fault tolerance mechanisms is introduced. Based upon an extensive set of experimental results along with probability of failure analysis, it was possible to show that the proposed fault tolerant scheme based on information redundancy leads to a better implementation and provides better SEU resistance than the traditional Triple Modular Redundancy (TMR). The fault tolerant cryptographic primitives introduced in this research are of crucial importance for the implementation of on-board security in spacecrafts.

Spacecrafts are extensively used by public and private sectors to support a variety of services. Considering the cost and the strategic importance of these spacecrafts, there has been an increasing demand to utilize strong cryptographic primitives to assure their security. Moreover, it is of utmost importance to consider fault tolerance in their designs due to the harsh environment found in space, while keeping low area and power consumption. The problem of recovering spacecrafts from failures or attacks, and bringing them back to an operational and safe state is crucial for reliability. Despite the recent interest in incorporating on-board security, there is limited research in this area. This research proposes a trusted hardware module approach for recovering the spacecrafts subsystems and their cryptographic capabilities after an attack or a major failure has happened. The proposed fault tolerant trusted modules are capable of performing platform restoration as well as recovering the cryptographic capabilities of the spacecraft. This research also proposes efficient fault tolerant architectures for the secure hash (SHA-2) and message authentication code (HMAC) algorithms. The proposed architectures are the first in the literature to detect and correct errors by using Hamming codes to protect the main registers. Furthermore, a quantitative analysis of the probability of failure of the proposed fault tolerance mechanisms is introduced. Based upon an extensive set of experimental results along with probability of failure analysis, it was possible to show that the proposed fault tolerant scheme based on information redundancy leads to a better implementation and provides better SEU resistance than the traditional Triple Modular Redundancy (TMR). The fault tolerant cryptographic primitives introduced in this research are of crucial importance for the implementation of on-board security in spacecrafts.

La protection des mécanismes cryptographiques constitue un enjeu important lors du développement d'un système d'information car ils permettent d'assurer la sécurisation des données traitées. Les supports utilisés étant à la fois logiciels et matériels, les techniques de protection doivent s'adapter aux différents contextes.Dans le cadre d'une cible logicielle, des moyens légaux peuvent être mis en oeuvre afin de limiter l'exploitation ou les usages. Cependant, il est généralement difficile de faire valoir ses droits et de prouver qu'un acte illicite a été commis. Une alternative consiste à utiliser des moyens techniques, comme l'obscurcissement de code, qui permettent de complexifier les stratégies de rétro-conception en modifiant directement les parties à protéger.Concernant les implantations matérielles, on peut faire face à des attaques passives (observation de propriétés physiques) ou actives, ces dernières étant destructives. Il est possible de mettre en place des contre-mesures mathématiques ou matérielles permettant de réduire la fuite d'information pendant l'exécution de l'algorithme, et ainsi protéger le module face à certaines attaques par canaux cachés.Les travaux présentés dans ce mémoire proposent nos contributions sur ces sujets tes travaux. Nous étudions et présentons les implantations logicielle et matérielle réalisées pour le support de courbes elliptiques sous forme quartique de Jacobi étendue. Ensuite, nous discutons des problématiques liées à la génération de courbes utilisables en cryptographie et nous proposons une adaptation à la forme quartique de Jacobi étendue ainsi que son implantation. Dans une seconde partie, nous abordons la notion d'obscurcissement de code source. Nous détaillons les techniques que nous avons implantées afin de compléter un outil existant ainsi que le module de calcul de complexité qui a été développé. / The protection of cryptographic mechanisms is an important challenge while developing a system of information because they allow to ensure the security of processed data. Since both hardware and software supports are used, the protection techniques have to be adapted depending on the context.For a software target, legal means can be used to limit the exploitation or the use. Nevertheless, it is in general difficult to assert the rights of the owner and prove that an unlawful act had occurred. Another alternative consists in using technical means, such as code obfuscation, which make the reverse engineering strategies more complex, modifying directly the parts that need to be protected.Concerning hardware implementations, the attacks can be passive (observation of physical properties) or active (which are destructive). It is possible to implement mathematical or hardware countermeasures in order to reduce the information leakage during the execution of the code, and thus protect the module against some side channel attacks.In this thesis, we present our contributions on theses subjects. We study and present the software and hardware implementations realised for supporting elliptic curves given in Jacobi Quartic form. Then, we discuss issues linked to the generation of curves which can be used in cryptography, and we propose an adaptation to the Jacobi Quartic form and its implementation. In a second part, we address the notion of code obfuscation. We detail the techniques that we have implemented in order to complete an existing tool, and the complexity module which has been developed.

Combiner les sources d'information pour créer un système de reconnaissance biométrique multimodal permet d'atténuer les limitations de chaque caractéristique utilisée, et donne l'opportunité d'améliorer significativement les performances. Le travail présenté dans ce manuscrit a été réalisé dans le but de proposer un système de reconnaissance performant, qui réponde à des contraintes d'utilisation grand-public, et qui puisse être implanté sur un système matériel de faible coût. La solution choisie explore les possibilités apportées par la multimodalité, et en particulier par la fusion du visage et de la paume. La chaîne algorithmique propose un traitement basé sur les filtres de Gabor, ainsi qu’une fusion des scores. Une base multimodale réelle de 130 sujets acquise sans contact a été conçue et réalisée pour tester les algorithmes. De très bonnes performances ont été obtenues, et ont été confirmées sur une base virtuelle constituée de deux bases publiques (les bases AR et PolyU). L'étude approfondie de l'architecture des DSP, et les différentes implémentations qui ont été réalisées sur un composant de type TMS320c64x, démontrent qu'il est possible d'implanter le système sur un unique DSP avec des temps de traitement très courts. De plus, un travail de développement conjoint d'algorithmes et d'architectures pour l'implantation FPGA a démontré qu'il était possible de réduire significativement ces temps de traitement. / Including multiple sources of information in personal identity recognition reduces the limitations of each used characteristic and gives the opportunity to greatly improve performance. This thesis presents the design work done in order to build an efficient generalpublic recognition system, which can be implemented on a low-cost hardware platform. The chosen solution explores the possibilities offered by multimodality and in particular by the fusion of face and palmprint. The algorithmic chain consists in a processing based on Gabor filters and score fusion. A real database of 130 subjects has been designed and built for the study. High performance has been obtained and confirmed on a virtual database, which consists of two common public biometric databases (AR and PolyU). Thanks to a comprehensive study on the architecture of the DSP components and some implementations carried out on a DSP belonging to the TMS320c64x family, it has been proved that it is possible to implement the system on a single DSP with short processing times. Moreover, an algorithms and architectures development work for FPGA implementation has demonstrated that these times can be significantly reduced.