<p>The compressive sensing (CS) paradigm provides an efficient image acquisition technique through simultaneous sensing and compression. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures are required to design cameras suitable for CS imaging.</p> <p>While this work is focused on the hardware implementation of CS encoding for CMOS sensors, the image reconstruction problem of CS is also studied. The energy compaction properties of the image in different domains are exploited to modify conventional reconstruction problems. Experimental results show that the modified methods outperform the 1-norm and TV (total variation) reconstruction algorithms by up to 2.5dB in PSNR.</p> <p>Also, we have designed, fabricated and measured the performance of two real-time and area-efficient implementations of the CS encoding for CMOS imagers. In the first implementation, the idea of active pixel sensor (APS) with an integrator and in-pixel current switches are used to develop a compact, current-mode implementation of CS encoding in analog domain. In another implementation, the conventional three-transistor APS structure and switched capacitor (SC) circuits are exploited to develop the analog, voltage-mode implementation of the CS encoding. With the analog and block-based implementation, the sensing and encoding are performed in the same time interval, thus making a real-time encoding process. The proposed structures are designed and fabricated in 130nm technology. The experimental results confirm the scalability, the functionality of the block read-out, and the validity of the design in making monotonic and appropriate CS measurements.</p> <p>This work also discusses the CS-CMOS sensors for high frame rate CS video coding. The method of multiple-camera with coded exposure video coding is discussed and a new pixel and array structure for hardware implementation of the method is presented.</p> / Doctor of Philosophy (PhD)

Cette thèse est élaborée en cotutelle entre l’université Badji Mokhtar (Laboratoire LERICA) et l’université de bourgogne (Laboratoire LE2I, UMR CNRS 5158). Elle constitue une contribution à l’étude et l’implantation de l’encodeur H.264/AVC. Durent l’évolution des normes de compression vidéo, une réalité sure est vérifiée de plus en plus : avoir une bonne performance du processus de compression nécessite l’élaboration d’équipements beaucoup plus performants en termes de puissance de calcul, de flexibilité et de portabilité et ceci afin de répondre aux exigences des différents traitements et satisfaire au critère « Temps Réel ». Pour assurer un temps réel pour ce genre d’applications, une solution reste possible est l’utilisation des systèmes sur puce (SoC) ou bien des systèmes multiprocesseurs sur puce (MPSoC) implantés sur des plateformes reconfigurables à base de circuit FPGA. L’objective de cette thèse consiste à l’étude et l’implantation des algorithmes de traitement des signaux et images et en particulier la norme H.264/AVC, et cela dans le but d’assurer un temps réel pour le cycle codage-décodage. Nous utilisons deux plateformes FPGA de Xilinx (ML501 et XUPV5). Dans la littérature, il existe déjà plusieurs implémentations du décodeur. Pour l’encodeur, malgré les efforts énormes réalisés, il reste toujours du travail pour l’optimisation des algorithmes et l’extraction des parallélismes possibles surtout avec une variété de profils et de niveaux de la norme H.264/AVC.Dans un premier temps de cette thèse, nous proposons une implantation matérielle d’un contrôleur mémoire spécialement pour l’encodeur H.264/AVC. Ce contrôleur est réalisé en ajoutant, au contrôleur mémoire DDR2 des deux plateformes de Xilinx, une couche intelligente capable de calculer les adresses et récupérer les données nécessaires pour les différents modules de traitement de l’encodeur. Ensuite, nous proposons des implantations matérielles (niveau RTL) des modules de traitement de l’encodeur H.264. Sur ces implantations, nous allons exploiter les deux principes de parallélisme et de pipelining autorisé par l’encodeur en vue de la grande dépendance inter-blocs. Nous avons ainsi proposé plusieurs améliorations et nouvelles techniques dans les modules de la chaine Intra et le filtre anti-blocs. A la fin de cette thèse, nous utilisons les modules réalisés en matériels pour la l’implantation Matérielle/logicielle de l’encodeur H.264/AVC. Des résultats de synthèse et de simulation, en utilisant les deux plateformes de Xilinx, sont montrés et comparés avec les autres implémentations existantes / This thesis has been carried out in joint supervision between the Badji Mokhtar University (LERICA Laboratory) and the University of Burgundy (LE2I laboratory, UMR CNRS 5158). It is a contribution to the study and implementation of the H.264/AVC encoder. The evolution in video coding standards have historically demanded stringent performances of the compression process, which imposes the development of platforms that perform much better in terms of computing power, flexibility and portability. Such demands are necessary to fulfill requirements of the different treatments and to meet "Real Time" processing constraints. In order to ensure real-time performances, a possible solution is to made use of systems on chip (SoC) or multiprocessor systems on chip (MPSoC) built on platforms based reconfigurable FPGAs. The objective of this thesis is the study and implementation of algorithms for signal and image processing (in particular the H.264/AVC standard); especial attention was given to provide real-time coding-decoding cycles. We use two FPGA platforms (ML501 and XUPV5 from Xilinx) to implement our architectures. In the literature, there are already several implementations of the decoder. For the encoder part, despite the enormous efforts made, work remains to optimize algorithms and extract the inherent parallelism of the architecture. This is especially true with a variety of profiles and levels of H.264/AVC. Initially, we proposed a hardware implementation of a memory controller specifically targeted to the H.264/AVC encoder. This controller is obtained by adding, to the DDR2 memory controller, an intelligent layer capable of calculating the addresses and to retrieve the necessary data for several of the processing modules of the encoder. Afterwards, we proposed hardware implementations (RTL) for the processing modules of the H.264 encoder. In these implementations, we made use of principles of parallelism and pipelining, taking into account the constraints imposed by the inter-block dependency in the encoder. We proposed several enhancements and new technologies in the channel Intra modules and the deblocking filter. At the end of this thesis, we use the modules implemented in hardware for implementing the H.264/AVC encoder in a hardware/software design. Synthesis and simulation results, using both platforms for Xilinx, are shown and compared with other existing implementations

This diploma’s thesis discourses the cryptographic systems and ciphers, whose function, usage and practical implementation are analysed. In the first chapter basic cryptographic terms, symmetric and asymetric cryptographic algorithms and are mentioned. Also usage and reliability are analysed. Following chapters mention substitution, transposition, block and stream ciphers, which are elementary for most cryptographic algorithms. There are also mentioned the modes, which the ciphers work in. In the fourth chapter are described the principles of some chosen cryptographic algorithms. The objective is to make clear the essence of the algorithms’ behavior. When describing some more difficult algorithms the block scheme is added. At the end of each algorithm’s description the example of practical usage is written. The chapter no. five discusses the hardware implementation. Hardware and software implementation is compared from the practical point of view. Several design instruments are described and different hardware design programming languages with their progress, advantages and disadvantages are mentioned. Chapter six discourses the hardware implementation design of chosen ciphers. Concretely the design of stream cipher with pseudo-random sequence generator is designed in VHDL and also in Matlab. As the second design was chosen the block cipher GOST, which was designed in VHDL too. Both designs were tested and verified and then the results were summarized.