ZnO has generated interest for flexible electronics/optoelectronic applications including transparent thin film transistors (TFTs). For this application, low temperature processes that simultaneously yield good electrical conductivity and optical transparency and that are compatible with flexible substrates such as plastic, are of paramount significance. Further, gate oxides are a critical component of TFTs, and must exhibit low leakage currents and self-healing breakdown in order to ensure optimal TFTs switching performance and reliability. Thus, the objective of this work was twofold: (1) develop an understanding of the processing-structure-property relationships of ZnO and high-κ BaTa2O6 and Al2O3 (2) understand the electronic defect structure of BaTa2O6 /ZnO and Al2O3/ZnO interfaces and develop insight to how such interfaces may impact the switching characteristics (speed and switching power) of TFTs featuring these materials. Of the ZnO films grown by atomic layer deposition (ALD), pulsed laser deposition (PLD) and magnetron sputtering at 100-200 °C, the latter method exhibited the best combination of n-type electrical conductivity and optical transparency. These determinations were made using a combination of photoluminescence, photoluminescence excitation, absorption edge and Hall measurements. Metal-insulator-semiconductor devices were then fabricated with sputtered ZnO and high-κ BaTa2O6 and Al2O3 and the interfaces of high-κ BaTa2O6 and Al2O3 with ZnO were analyzed using frequency dependent C-V and G-V measurements. The insulator films were deposited at room temperature by magnetron sputtering using optimized processing conditions. Although the Al2O3 films exhibited a lower breakdown strength and catastrophic breakdown behavior compared to BaTa2O6/ZnO interface, the Al2O3/ZnO interface was characterized by more than an order of magnitude smaller density of interface traps and interface trapped charge. The BaTa2O6 films in addition were characterized by a significantly higher concentration of fixed oxide charge. The transition from accumulation to inversion in the Al2O3 MIS structure was considerably sharper, and occurred at less than one tenth of the voltage required for the same transition in the BaTa2O6 case. The frequency dispersion effects were also noticeably more severe in the BaTa2O6 structures. XPS results suggest that acceptor-like structural defects associated with oxygen vacancies in the non-stoichiometric BaTa2O6 films are responsible for the extensive electrical trapping and poor high frequency response. The Al2O3 films were essentially stoichiometric. The results indicate that amorphous Al2O3 is better suited than BaTa2O6 as a gate oxide for transparent thin film transistor applications where low temperature processing is a prerequisite, assuming of course that the operation voltage of such devices is lower than the breakdown voltage. Also, the operation power for the devices with amorphous Al2O3 is lower than the case for devices with BaTa2O6 due to the smaller fixed oxide charges and interface trap density.

The continuous downscaling has enforced the device size and oxide thickness to few nanometers. After serving for several decades as an excellent gate oxide layer in complementary metal oxide semiconductor (CMOS) devices, the thickness of SiO2 layer has reached to its theoretical limits. Ultra-thin films of SiO2 can result in severe leakage currents due to direct tunneling as well as maintaining the homogeneity of the layers becomes an additional challenge. The use of a high- (HK) layer can solve these twin concerns of the semiconductor industry, which can also enhance the capacitance due to superior dielectric permittivity and reduce the leakage current by being thicker than the silicon dioxide. This thesis is concerned about the development of solution route fabricated high-k (TiO2, ZrO2 and HfO2) gate dielectrics and the investigation of high-/silicon interfaces by highly sensitive DLTS technique in MOS structures. The solution processing reduce the industrial fabrication cost and the DLTS method has the advantage to accurately measure the interface related defects parameters; such as interface trap density (Dit), capture cross-section (), activation energy (ET) and also distinguish between bulk and interface traps. In this thesis, HK films have been deposited by solution route, the material and electrical properties of the film and the HK/Si interface have been extensively evaluated. IN CHAPTER 1, we have summarized the history and evolution of transistor and it provides the background for the work presented in this thesis. IN CHAPTER 2, we have described the experimental method /technique used for the fabrication and characterization. The advantages and working principals of spin-coating and DLTS techniques are summarized. IN CHAPTER 3, we have presented the preparation and optimization of TiO2 based HK layer. Structural, surface morphology, optical electrical and dielectric properties are discussed in details. A high- 34 value is achieved for the 36 nm TiO2 films. IN CHAPTER 4, we presented the technologically relevant Si/TiO2 interface study by DLTS technique. The DLTS analysis reveals a small capture cross-section of the interface with acceptable interface state density. IN CHAPTER 5, we have focused on the fabrication of amorphous ZrO2 films on p-Si substrate. The advantage of amorphous dielectric layer is summarized as first dielectric reported SiO2 is used in its amorphous phase. The moderate-15 with low leakage current density is achieved. IN CHAPTER 6, the HfO2 films are prepared using hafnium isopropoxide and a high value of dielectric constant 23 is optimized with low leakage current density. The current conduction mechanisms are discussed in details. IN CHAPTER 7, we have probed the oxygen vacancy related sub-band-gap states in HfO2 by DLTS technique. IN CHAPTER 8, we have presented the summary of the dissertation and the prospect research directions are suggested. In summary, we have studied the group IVB transition metal elemental oxides (TMEO); TiO2, ZrO2 and HfO2 thin films in the MOS structure, as a possible replacement of SiO2 gate dielectric. For the TMEO films deposition a low-cost and simple method spin-coating was utilized. The film thicknesses are in the range of 35 – 39 nm, which was measured by ellipsometry and confirmed with the cross-sectional SEM. A rough surface of gate dielectric layer can trap the charge carrier and may cause the Fermi level pinning, which can cause the threshold voltage instabilities. Hence, surface roughness of oxide layer play an important role in CMOS device operation. We have achieved quite good flat surfaces (RMS surface roughness’s are 0.2 – 2.43 nm) for the films deposited in this work. The TiO2 based MOS gate stack shows an optimized high dielectric constant ( 34) with low leakage current density (3.710-7 A.cm-2 at 1 V). A moderate dielectric constant ( 15) with low leakage current density (4.710-9 A.cm-2 at 1 V) has been observed for the amorphous ZrO2 thin films. While, HfO2 based MOS gate stack shows reasonably high dielectric constant ( 23) with low leakage current density (1.410-8 A.cm-2 at 1 V). We have investigated the dominating current conduction mechanism and found that the current is mainly governed by space charge limited conduction (SCLC) mechanism for the high bias voltages, while low and intermediate bias voltages show the (Poole – Frenkel) PF and (Fowler – Nordheim) FN tunneling, respectively. For the HfO2 MOS device band alignment is drawn from the UPS and J-V measurements. The band gap and electron affinity of HfO2 films are estimated 5.9 eV and 3 eV, respectively, which gives a reasonable conduction band offset (1.05 eV) with respect to Si. A TMEO film suffers from a large number of intrinsic defects, which are mostly oxygen vacancies. These defects can create deep levels below the conduction band of high- dielectric material, which can act like a hole and electron traps. In addition to that, interface between Si and high- is an additional concern. These defect states in the band gap of high- or at the Si/ high- interface might lead to the threshold voltage shifts, lower carrier mobility in transistor channel, Fermi level pinning and various other reliability issues. Hence, we also studied bulk and interfacial defects present in the high- films on Si and their interface with Si by a very sensitive DLTS technique. The capture cross-sections are measured by insufficient filling DLTS (IF – DLTS). The defects present at the interface are Si dandling bond and defect in the bulk are mostly oxygen vacancies related defects present in various charge states. The interface states (Dit) are in the range of 2×1011 to 9×1011 eV-1cm-2, which are higher than the Al/SiO2/Si MOS devices (Dit in Al/SiO2/Si is the benchmark and in the order of 1010 eV-1cm-2). Still this is an acceptable value for Si/high-k (non-native oxide) MOS devices and consistent with other deposition methods. The capture cross-sections are found to be quite low in the order of 10-18 to 10-19 cm2, which indicate a minor impact on the device operation. The small value of capture cross-sections are attributed to the involvement of tunneling, to and from the bulk traps to the interface. In conclusion, the low cost solution processed high- thin films obtained are of high quality and find their importance as a potential dielectric layer. DLTS study will be helpful to reveal various interesting facts observed in high- such as resistive switching, magnetism and leakage current problems mediated by oxygen vacancy related defects

Hafnium based high-κ dielectrics are considered potential candidates to replace SiO2 or SiON as the gate dielectric in complementary metal oxide semiconductor (CMOS) devices. Hydrogen is one of the most significant elements in semiconductor technology because of its pervasiveness in various deposition and optimization processes of electronic structures. Therefore, it is important to understand the properties and behavior of hydrogen in semiconductors with the final aim of controlling and using hydrogen to improve electronic performance of electronic structures. Trap transformations under annealing treatments in hydrogen ambient normally involve passivation of traps at thermal SiO2/Si interfaces by hydrogen. High-κ dielectric films are believed to exhibit significantly higher charge trapping affinity than SiO2. In this thesis, study of hydrogen trapping in alternate gate dielectric candidates such as HfO2 during annealing in hydrogen ambient is presented. Rutherford backscattering spectroscopy (RBS), elastic recoil detection analysis (ERDA) and nuclear reaction analysis (NRA) were used to characterize these thin dielectric materials. It was demonstrated that hydrogen trapping in bulk HfO2 is significantly reduced for pre-oxidized HfO2 prior to forming gas anneals. This strong dependence on oxygen pre-processing is believed to be due to oxygen vacancies/deficiencies and hydrogen-carbon impurity complexes that originate from organic precursors used in chemical vapor depositions (CVD) of these dielectrics.

Les semiconducteurs III-V ayant des propriétés électroniques et optiques très intéressantes, leur intégration sur Si permettrait la combinaison de fonctionnalités variées sur la même puce, une solution potentielle aux obstacles affrontés par les composants CMOS. Les travaux pionniers de McKee et al ont démontré que le SrTiO3 (STO) peut être directement épitaxié sur Si par EJM (Epitaxie par Jets Moléculaires). Plus tard, une équipe de Motorola a montré qu’il était possible d’épitaxier des couches minces de GaAs sur des templates de STO/Si, ouvrant une voie nouvelle pour l’intégration monolithique de III-V sur Si. Sur cette base, l’INL a entrepris l’étude de la croissance de semiconducteurs III-V sur STO. Il a notamment été montré que la faible adhésion caractéristique de ces systèmes favorisait un mode d’accommodation spécifique du désaccord paramétrique par la formation d’un réseau de dislocations confinées à l’interface entre les deux matériaux sans défauts traversant liés à une relaxation plastique, ce qui ouvre des perspectives intéressantes pour l’intégration monolithique de III-V sur Si. Dans ce contexte, lors de cette thèse, Nous nous sommes d’abord focalisé sur l’optimisation de la croissance des templates de STO/Si. Nous avons en particulier montré qu’une couche de STO relaxée et riche en oxygène favorisait la reprise de croissance de l’InP. Nous avons ensuite étudié de manière systématique la croissance d’InP sur STO. La faible adhésion caractéristique de ce système conduit à la formation d’îlots aux premiers stades de la croissance, ainsi qu’à l’observation d’une compétition entre plusieurs orientations cristallines de l’InP. Nous avons fixé des conditions de croissance et de préparation de la surface de STO permettant d’obtenir des îlots purement orientés (001). Nous avons ensuite optimisés l’étape de coalescence de ces îlots pour former des couches 2D d’InP intégrées sur STO/Si. Une étude structurale et optique complète de ces hétérostructures, nous a permis d’analyser le potentiel de notre approche et pointer certaines limitations des templates de STO/Si. Sur cette base, nous avons enfin initié l’étude de templates alternatifs pour la croissance d’InP, en effectuant quelques études préliminaires de l’épitaxie d’InP sur substrats de LaAlO3. / Due to their electrical and optical properties, the integration of III-V semiconductors on Si would open the path to the combination of a various functionalities on the same chip, a potential solution to the challenges faced by CMOS components. The pionner studies by McKee and al have shown that SrTiO3 (STO) could be directly epitaxied on Si by MBE (Molecular Beam Epitaxy). Few years later, a Motorola team has shown that it is possible to epitaxy thin GaAs layers on STO/Si templates, hence opening a new path for III-V monolithic integration on Si. Based on this, the INL has undertaken the study of III-V semiconductors growth on STO. In particular, it has been shown that the weak adhesion specific to these systems favors a preferential accommodation mode of the lattice mismatch by breaking interfacial bonds rather than by plastic relaxation of an initially compressed layer. Hence, it is possible in spite of a strong lattice mismatch to grow III-V semiconductors without threading defects related to a plastic relaxation mechanism, which opens interesting perspectives for IIIV monolithic integration on Si. In this context, during this thesis, we have focalised in the beginning on optimising the growth of the STO/Si templates. In particular, we have shown that a relaxed and oxygen-rich STO layer favors undertaking InP growth. Next, we have studied systematically the InP growth on STO. The weak adhesion specific to this system leads to islands formation at the early stages of growth, as well as the observation of a competition between different crystalline orientations of the InP islands. We have worked out STO growth conditions and surface preparation strategies that allow obtaining purely (001) oriented InP islands. We have next optimised the islands coalescence step in order to form 2D InP layers on STO/Si. Based on a complete structural and optical study of these heterostructures, we have been able to analyse our approach’s potential and to point out cetain limitations of the STO/Si templates. On this basis, we have finally initiated the study of alternative templates for InP growth, by undergoing some preliminary studies of InP epitaxy on LaAlO3 substrates.

The demands for faster, smaller, and less expensive electronic equipments are basically the driving forces for improving the speed and increasing the packing density of microelectronic components. Down-scaling of the devices is the principal method to realize these requests. For future CMOS devices, new materials are required in the transistor structure to enable further scaling and improve the transistor performance. This thesis focuses on novel metal gate and high-κ dielectric materials for future CMOS technologies. Specifically, TiN and ZrN gate electrode materials were studied with respect to work function and thermal stability. High work function, suitable for pMOS transistors, was extracted from both C-V and I-V measurements for PVD and ALD TiN in TiN/SiO2/Si MOS capacitor structures. ZrNx/SiO2/Si MOS capacitors exhibited n-type work function when the low-resistivity ZrNx was deposited at low nitrogen gas flow. Further, variable work function by 0.6 eV was achieved by reactive sputter depositing TiNx or ZrNx at various nitrogen gas flow. Both metal-nitride systems demonstrate a shift in work function after RTP annealing, which is discussed in terms of Fermi level pinning due to extrinsic interface states. Still, the materials are promising in a gate last process as well as show potential as complementary gate electrodes. The dielectric constant of as-deposited (Ta2O5)1-x(TiO2)x thin films is around 22, whereas that of AlN is about 10. The latter is not dependent on the degree of crystallinity or on the measurement frequency up to 10 GHz. Both dielectrics exhibit characteristics appropriate for integrated capacitors. Finally, utilization of novel materials were demonstrated in strained SiGe surface-channel pMOSFETs with an ALD TiN/Al2O3 gate stack. The transistors were characterized with standard I-V, charge pumping, and low-frequency noise measurements. Correlation between the mobility and the oxide charge was found. Improved transistor performance was achieved by conducting low-temperature water vapor annealing, which reduced the negative charge in the Al2O3.

In recent years, advanced high κ gate dielectrics are under serious consideration to replace SiO2 and SiON in semiconductor industry. Hafnium-based dielectrics such as hafnium oxides, oxynitrides and Hf-based silicates/nitrided silicates are emerging as some of the most promising alternatives to SiO2/SiON gate dielectrics in complementary metal oxide semiconductor (CMOS) devices. Extensive efforts have been taken to understand the effects of hydrogen impurities in semiconductors and its behavior such as incorporation, diffusion, trapping and release with the aim of controlling and using it to optimize the performance of electronic device structures. In this dissertation, a systematic study of hydrogen trapping and the role of carbon impurities in various alternate gate dielectric candidates, HfO2/Si, HfxSi1-xO2/Si, HfON/Si and HfON(C)/Si is presented. It has been shown that processing of high κ dielectrics may lead to some crystallization issues. Rutherford backscattering spectroscopy (RBS) for measuring oxygen deficiencies, elastic recoil detection analysis (ERDA) for quantifying hydrogen and nuclear reaction analysis (NRA) for quantifying carbon, X-ray diffraction (XRD) for measuring degree of crystallinity and X-ray photoelectron spectroscopy (XPS) were used to characterize these thin dielectric materials. ERDA data are used to characterize the evolution of hydrogen during annealing in hydrogen ambient in combination with preprocessing in oxygen and nitrogen.

Afin de continuer l'amélioration des performances du transistor MOSFET à l'échelle décananométrique, la recherche en microélectronique explore différentes solutions. Les travaux menés au cours de cette thèse se sont plus particulièrement orientés vers l'étude de transistors innovants avec une architecture Double-Grille (DGMOSFET) et l'utilisation de “nouveaux” matériaux tels que les diélectriques de grille à forte permittivité dits “high-κ” et les semiconducteurs à forte mobilité intrinsèque (Ge et III-V). Grâce au développement de codes de simulation numérique basés sur la résolution auto-cohérente du couple d'équations Poisson-Schrödinger ou en utilisant le formalisme des fonctions de Green (NEGF), nous étudions le comportement électrique de différentes structures. Dans un premier temps, le fonctionnement des capacités Métal-Isolant-Semiconducteur et Métal-Isolant-Métal est simulé afin d'évaluer l'influence des propriétés des matériaux innovants et de la composition de l'empilement de grille sur les caractéristiques capacité-tension et sur le courant de fuite tunnel à travers la grille. Puis, les performances en termes de courant de drain face à la réduction de la longueur de grille (effets électrostatiques) et de l'épaisseur du canal de conduction (effet de confinement quantique) sont comparées dans le transistor MOS Double-Grille (à grilles indépendantes ou connectées) avec plusieurs matériaux aux propriétés très différentes (Si, Ge, GaAs et In0.53Ga0.47As). Enfin, nous avons développé une approche simplifiée (modélisation compacte) pour le calcul du courant de drain en dérive-diffusion ou balistique dans les transistors MOS Double-Grille à grilles indépendantes, validée par nos codes de simulation numérique.

Nos travaux concernent la modélisation des structures MOS affectées par des défauts qui détériorent leurs propriétés électriques et par conséquent celles des dispositifs mémoires. Nous avons attaché une grande importance à la compréhension des phénomènes liés à la miniaturisation de la capacité et du transistor MOS qui sont les composants électroniques élémentaires des mémoires. Nos modèles basés sur de nombreuses études réalisées sur ces sujets, représentent de nouveaux outils d'analyses pour créer les modèles de base décrivant le fonctionnement plus complexe des dispositifs mémoires. Après un rappel des notations et des équations de base utilisées pour les capacités MOS et les transistors MOS, nous retraçons l'évolution des dispositifs mémoires jusqu'aux mémoires à nanocristaux. Dans une deuxième partie de notre travail, nous décrivons les différentes modélisations de la capacité MOS développées en fonction de l'effet parasite considéré : la poly-désertion de la grille, la non uniformité du dopage du substrat, de l‘épaisseur d'oxyde et des charges fixes présentes dans la couche d'isolant. Nous avons ainsi pu proposer une méthode de détermination de la répartition de la charge générée dans l'oxyde par des stress électriques ainsi qu'une analyse de l'origine de ces charges. La troisième partie est consacrée aux modélisations du transistor MOS basées sur une approche segmentée. Celle-ci a été appliquée à l'étude des résistances séries et aux modélisations des dopages (grille et substrat), puis étendue à la modélisation des transistors à isolants ultra-minces. Nous présentons notamment les modifications de la caractéristique IDS(VGS,VDS) du transistor MOS induites par les non uniformités énumérées ci-dessus. Enfin, nous appliquons nos modèles aux mémoires à nanocristaux de silicium. Nous proposons une modélisation de la charge localisée dans les nodules proches du drain, ce qui nous a permis de développer un modèle simulant l'opération d'écriture de ces mémoires. Les caractérisations électriques de ces structures à piégeages discrets sont également analysées à l'aide de nos modèles.

Les semiconducteurs III-V ayant des propriétés électroniques et optiques très intéressantes, leur intégration sur Si permettrait la combinaison de fonctionnalités variées sur la même puce, une solution potentielle aux obstacles affrontés par les composants CMOS. Les travaux pionniers de McKee et al ont démontré que le SrTiO3 (STO) peut être directement épitaxié sur Si par EJM (Epitaxie par Jets Moléculaires). Plus tard, une équipe de Motorola a montré qu'il était possible d'épitaxier des couches minces de GaAs sur des templates de STO/Si, ouvrant une voie nouvelle pour l'intégration monolithique de III-V sur Si. Sur cette base, l'INL a entrepris l'étude de la croissance de semiconducteurs III-V sur STO. Il a notamment été montré que la faible adhésion caractéristique de ces systèmes favorisait un mode d'accommodation spécifique du désaccord paramétrique par la formation d'un réseau de dislocations confinées à l'interface entre les deux matériaux sans défauts traversant liés à une relaxation plastique, ce qui ouvre des perspectives intéressantes pour l'intégration monolithique de III-V sur Si. Dans ce contexte, lors de cette thèse, Nous nous sommes d'abord focalisé sur l'optimisation de la croissance des templates de STO/Si. Nous avons en particulier montré qu'une couche de STO relaxée et riche en oxygène favorisait la reprise de croissance de l'InP. Nous avons ensuite étudié de manière systématique la croissance d'InP sur STO. La faible adhésion caractéristique de ce système conduit à la formation d'îlots aux premiers stades de la croissance, ainsi qu'à l'observation d'une compétition entre plusieurs orientations cristallines de l'InP. Nous avons fixé des conditions de croissance et de préparation de la surface de STO permettant d'obtenir des îlots purement orientés (001). Nous avons ensuite optimisés l'étape de coalescence de ces îlots pour former des couches 2D d'InP intégrées sur STO/Si. Une étude structurale et optique complète de ces hétérostructures, nous a permis d'analyser le potentiel de notre approche et pointer certaines limitations des templates de STO/Si. Sur cette base, nous avons enfin initié l'étude de templates alternatifs pour la croissance d'InP, en effectuant quelques études préliminaires de l'épitaxie d'InP sur substrats de LaAlO3.