This work demonstrates the design and implementation of a digitally encoded Sinusoidal Pulse Width Modulation strategy for the switching of bi-directional secondary side power switches of an AC-link. Through this method, high frequency (200 kHz) half sinusoid or haversine voltage pulses produced by the Parallel Loaded Resonant converter working in discontinuous mode at primary side are converted to low frequency (400/60/50 Hz) waveforms at the output. This control strategy allows the converter to operate at high power density, as soft switching (ZCS/ZVS) is possible at both the turn-on and turn-off of switches. Also through this strategy the output waveform at load will have low Total Harmonic Distortion (THD).

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<p> This thesis focuses on the noise model verification at both device and circuit levels using circuit simulators. The techniques and procedures developed in this thesis are general and can be applied to any proposed RF noise model equations. To fulfil the two tasks, three main topics have been accomplished. First, a general noise source implementation method has been presented in detail in this thesis and is verified with measurements for both long and short-channel MOSFETs. This method provides a simple and effective way to implement the enhanced channel noise and induced gate noise of MOSFETs without increasing the simulation complexity for the simulators.</p> <p> Second, a systematic procedure to refine the model parameters used in noise calculation is presented. For a model to accurately predict the HF noise characteristics, the accuracy in the prediction of both DC and AC characteristics has to be ensured. The procedure proposed in this thesis provides both DC and AC model parameter verification and optimization for RF noise simulation purpose.</p> <p> Third, as for benchmark circuits to verify noise model at the circuit level, two LNA designs are proposed in the thesis. The first design gives the emphasis on the noise reduction technique and the LNA design procedure. The proposed noise reduction technique gives circuit designers more control on noise figure minimization through noise matching. The second design is used to experimentally verify the noise model at the circuit level.</p> / Thesis / Master of Applied Science (MASc)

Microprocessors in today's computers continue to get faster and more powerful. From the Intel 80X86 series to today's Pentium IV, CPUs have greatly improved in performance. Accordingly, their power consumption has increased dramatically [1][2]. An evolution began in power loss reduction when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. In order to provide the power as quickly as possible, the voltage regulator (VR), a dedicated DC-DC converter, is placed in close proximity to power the processor. At first, VRs drew power from the 5V output of the silver box. As the power delivered through the VR increased so dramatically, it became no longer efficient to use the 5V bus. Then for desktop and workstation applications, the VR input voltage moved to the 12V output of the silver box. For laptop application, the VR input voltage range covers the battery voltage range and the adaptor voltage. In the meantime, microprocessors will run at very low voltage (sub 1V), and will consume up to 150A of current, and will have dynamics of about 400A/us. The current VR solution is the 12V-input multiphase interleaved buck converter. The switching frequency is around 300KHz. This approach has several limitations for the future. OSCON capacitor is one limitation due to its large ESR and ESL; the low switching frequency the second limitation and the large inductance is the third limitation. Analysis shows that the all-ceramic solution is a better solution than the OSCON solution when the VR switching frequency reaches 1MHz. However, the 12V-input multiphase buck converter suffers low efficiency at high switching frequency, which rules out a legitimate chance of the current VR topology benefiting from high switching frequency. The extreme duty cycle is the fundamental reason why the 12V-input multiphase buck converter is not suitable for future VRs. Employing the transformer concept can extend duty cycle, and therefore offer an opportunity to improve efficiency. The push-pull buck (PPB) converter is proposed as a solution. The efficiency is improved compared with the buck converter. Integrated magnetic techniques can be used to further improve the efficiency and simplify the implementation. The impact of transformer concept on transient response is analyzed. The PPB converter efficiency is still not satisfactory at 1MHz due to the switching loss. Switching loss being a barrier, soft switching is needed. The proposed soft-switched phase-shift buck (PSB) converter achieves soft switching for the top switches. Highly efficient power conversion is achieved at high switching frequency. The integrated magnetics makes the implementation concise and delivers good performance. Given that the PSB converter has good performance, the matrix-transformer phase-shift buck (MTPSB) converter is a simplified version of the four-phase PSB converter. The MTPSB converter trades off some performance with circuit complexity. This feature establishes itself as a very cost-effective solution for future VRs. The magnetic structure of the MTPSB converter is also very simple with the use of integrated magnetics. Mobile CPUs are used in laptop computers. They require very challenging power management. The challenges for a laptop VR are different from and greater than those for a desktop VR. A laptop VR needs to have high efficiency at both heavy load and light load, good transient response and small and light form-factor, and work well with the wide input voltage range. Future mobile CPUs demand very aggressive power. The current single-stage VR approach cannot provide a suitable solution for the future. The PSB converter has disadvantages in light-load efficiency and does not work well with wide input voltage range; therefore it is not a suitable solution for laptop VRs although it is still a suitable solution for desktop VRs. The two-stage approach solves the wide-input-voltage-range issue and improves efficiency at heavy load significantly. The intermediate bus voltage Vbus is a very important parameter impacting overall efficiency. There is not one optimal Vbus value for all load conditions. The heavier the load, the higher the optimal Vbus. Based on this fact, the ABVP control is proposed. Vbus is adaptively positioned according to the load current therefore optimal Vbus is achieved under most conditions. Experimental results verify the theoretical prediction. The ONP control is another control scheme proposed to improve the light-load efficiency. By selecting optimal number of phases based on mobile processor power states, the VR light-load efficiency is improved. Experimental results show the proof. The baby-buck concept is the third concept proposed to improve the very-light-load efficiency. By operating the baby-buck channel, the two-stage VR improves efficiency at very light load. The two-stage VR featuring the three proposed control schemes has much higher efficiency than the single-stage VR over a very wide load range; therefore the battery life is extended. The two-stage VR with the proposed control schemes is a good solution for future laptop VRs. The problem solving process in this work proves that good solutions in isolated converters can be modified to fit into the non-isolated application. Non-isolated converters and isolated converters are not two separated worlds. On the contrary, these two worlds have many things in common. Good concepts can be transplanted from one world to another with minor modification and many problems can be solved this way. Another proven point in this work is that sometimes the solution is a fundamental, such as the change of power delivery architecture. One should not be limited by what is available right now, and should think outside the box. Once a fundamental change is made, it is very beneficial to take full advantage of the change, as it provides new opportunities. / Ph. D.

It is perceived that Moore's Law will prevail at least for the next decade with the continuous advancement of processing technologies for integrated circuits. According to Intel's roadmap, over one billion transistors will be integrated in one processor by the year 2010; the processor's clock speed will approach 15 GHz; the core static currents will increase up to 200 A; the dynamic current slew rate will rise up to 250 A/ns; and the core voltage will decrease to 0.8 V. The rapid advancement of processor technology has posed stringent challenges to power management for both an efficient power delivery and an accurate voltage regulation. The primary objectives of this dissertation are to understand the fundamental limitations of the state-of-the-art solution for the power management, and hence to support possible solutions for meeting the power requirement of the next generations of processors. First, today's voltage-regulator module (VRM) design, which is based on the multiphase interleaving buck topology, is thoroughly analyzed. The analysis results of the control bandwidths versus the VRM transient voltage spikes highlight the trend of high-frequency VRM design for smaller size and faster transient response. Based on the concept of achieving constant VRM output impedance, design guidelines are proposed for different kinds of control methods. However, the high switching-related losses in the conventional multiphase buck converter limit its further applications. This dissertation proposes a series of new topologies in order to break through the barriers by applying an inductor-coupling or autotransformer structure to reduce the switching-related losses by extending the duty cycle. Then, this dissertation pushes the topology innovation further by introducing soft-switching quasi-resonant converters for the VRM design. The combination of the quasi-resonant and active-clamped concepts derives a family of new converters, which can eliminate all the switching and body-diode losses. The experimental results at 1-2MHz switching frequencies prove that the proposed solutions for the VRM design can realize very high efficiency and high power density. / Ph. D.

It is perceived that Moore's Law will prevail at least for the next decade, with continuous advancements of processing technologies for very-large-scale integrated (VLSI) circuits. Nano technology is driving VLSI circuits in a path of greater transistor integration, faster clock frequency, and lower operation voltage. This has imposed a new challenge for delivering high- quality power to modern processors. Power management technology is critical for transferring the required high current in a highly efficient way, and accurately regulating the sub-1V voltage in very fast dynamic transient response conditions. Furthermore, the VRs are limited in a given area and the power density is important to save the precious real estate of the motherboard. Based on the power delivery path model, the analysis results show that as long as the bandwidth can reach around 350 kHz, the bulk capacitor of the VR can be completely eliminated, which means significant savings in cost and real estate. Analysis also indicates that 650kHz bandwidth can reduce the number of the decoupling capacitor from 230 to 50 for future microprocessor case. Beyond 650kHz, the reduction is not obvious any more due to the parasitic components along the power delivery path. Following the vision of high bandwidth, the VRs need to operate at much higher frequency than today's practice. Unfortunately, the multiphase buck converter cannot benefit from it due to the low efficiency at high switching frequency. The extreme duty is the bottleneck. The extreme duty cycle increases VR switching loss, reverse recovery loss, and conduction loss; therefore makes the 12V-input VR efficiency drop a good deal when compared with 5V-input VR efficiency. Two-stage approach is proposed in this dissertation to solve this issue. The analysis shows that the two-stage conversion has much better high frequency capability than the conventional single stage VRs. Based on today's commercial devices, 2-MHz is realized by the hardware and 350kHz bandwidth is achieved to eliminate the output bulk capacitors. Further improvement based on future devices and several proposed methods of reducing switching loss and body diode loss can push the switching frequency up to 4MHz while maintaining good efficiency. Such a high frequency makes the high bandwidth design (650kHz) feasible. Hence, the output capacitance can be significantly reduced to save cost and real estate. The two-stage concept is also effective in laptop computer and 48V DPS applications. It has been experimentally proved that two-stage VR is able to achieve higher switching frequency than single stage not only at full load condition but also at light load condition by the proposed ABVP and AFP concept based on two-stage configuration. These unique control strategies make the two-stage approach even more attractive. As the two-stage approach is applied to 48V DPS applications, such as telecommunication system and server systems, more efficient and higher power density power supply can be achieved while greatly cut down the cost. Therefore, after the two-stage approach is proposed, it has been widely adopted by the industry. In order to further reduce the output capacitance, the power architecture of computer needs to be modified. Based on two-stage approach, one possible solution is to move the second stage VR up to the OLGA board. Based on this structure, the parasitics can be dramatically reduced and the number of the cavity capacitor is reduced from 50 to 14. By reducing ESL of the capacitor, the output capacitance could be further reduced. After that and based on two-stage approach again, VR+LR structure is discussed, which provides the opportunity to reduce the output capacitance and integrate the power supply with CPU. The feasibility is studied in this dissertation from both power loss reduction and output capacitance reduction perspectives. Experimental results prove that LR can significantly reduce the voltage spike while minimizing the output capacitance. As a conclusion, the two-stage approach is a promising solution for powering future processors. It is widely effective in computer and communication systems. Far beyond that, it provides a feasible platform for new architectures to power the future microprocessors. / Ph. D.

As a racecar negotiates a track, it is subjected to many inputs at both high and low frequencies. These inputs come from the track surface, the motion of the body, and from aerodynamic disturbances. The damper's ability to control these inputs leads to improved grip at the tires, which increases overall handling of the vehicle. Since dampers have always been assumed to be primarily velocity dependent, little work has gone into exploring damper's frequency dependent nature. Therefore, this study evaluates the effect input frequency has on the damper's output force. Utilizing experimental testing, with a state of the art damper dynamometer, and computer simulation with a parametric damper model developed for this study, several inputs and key parameters are tested, and the damper's frequency dependent nature starts to emerge. Constant peak velocity sinusoidal and sinusoidal sweep inputs are used for the experimental testing. The results show that as the input frequency is increased, the damper's output force lissajou transitions from the characteristic shape of a damper's lissajou to a shape characteristic of a spring's lissajou. This change in the lissajou is linked to hysteretic effects, which includes the gas spring effect. Damper parameters that are suspected to contribute to the hysteretic effects are explored with computer simulation and additional experimental testing. The results from this show that fluid preparation, fluid type, initial gas pressure, and friction have a predictable effect on the damper's output force. / Master of Science

The concrete maturity method can be utilized to determine in situ strength of concrete. It uses the temperature of concrete to determine a maturity index that can then be used to determine strength of concrete. However, monitoring the concrete temperature using thermocouples brings up a wiring issue, which is not advisable in an equipment and human intensive area like a construction site. One of the ways to get around this wiring issue is to use Radio Frequency Identification (RFID) technology, which is capable of transmitting information wirelessly. Previous research implemented using ultra high frequency RFID tags embedded in fresh concrete found that water could be the impediment for transmitting RFID signal from within concrete during early stages of curing. From literature it was found that lower the frequency, better the chances of the wave penetrating water. The objective of the research was to figure out whether the frequency of RFID tags has any relationship with the readability of RFID tags embedded in fresh concrete. For this investigation, low frequency, high frequency, and ultra high frequency RFID tags were tested within fresh concrete to see any difference between tags in terms of transmitting information. This experiment was carried out in a controlled space to reduce the number of variables affecting the experiment outcome. The low frequency, high frequency, and ultra high frequency RFID tags were placed within 2 in x 3 in x 2 in wooden formwork at a depth of 4 in, 8 in, and 12 in. Ready mix concrete was poured into the formwork and 3 concrete cubes were cast with the tags embedded within them. Readers that could be connected to a laptop were used to monitor and collect the time at which these RFID tags can be detected. The test showed that the RFID signals from the low frequency tags at all depths were detected as soon as concrete was poured. The Ultra High Frequency tags placed at the 4" level could be detected 15 minutes after concrete was poured. The UHF tags at the 8" level could be detected after 30 minutes. The UHF tags at the 12" level took on an average 2 hours to be detected from the vicinity of the formwork. The greater the depth at which the ultra high frequency tag was buried the longer it took for it to be detected. The high frequency tags could be detected only at the 4" level. The reason the performance of the HF card degraded in concrete could be because it uses an aluminum foil antenna which is more susceptible to the environment changing the relative permeability. A copper wire antenna could have fared better in this condition, increasing the chances of detecting the tag. Moreover a passive tag was used. The read range and chances of detection could have been increased had an active tag been used. The power of the reader that was used was also very less which might have contributed to the tag not being detected. Among the tags that were used in the experiment it was found that low frequency tags was the tag that could be detected the earliest after concrete was poured into the forms. However, the maximum read range of the tag observed in the experiment was 20" which is too small a distance to be used on an actual construction site.

Alternative means of satisfying the high bandwidth and protected communications requirements for New Construction Naval Surface Ships in the midst of conflicting reduced radar cross section (RCS) requirements were investigated using the systems engineering process. <p>Various antenna, ranging from parabolic dish antennas to Luneberg lens antennas to phased array antennas, and feed and amplifier combinations were considered to provide a dual-band Super High Frequency (SHF) and Extremely High Frequency (EHF) Satellite Communications (SATCOM) Terminal (SEST). <p>Through the design of this hypothetical system, the various stages of the systems engineering process are considered-- definition of need, conceptual design, preliminary system design, production and installation, and utilization and support. Sample tasks are performed at each stage in the process (e.g., a system performance specification is prepared in the advanced system planning stage). <p>The set of technical solutions that remained in the preliminary design phase are compared based on life cycle costs. Two approaches are recommended -- one assuming lowest life cycle cost has highest priority and one assuming that the ability to communicate simultaneously on SHF and EHF has highest priority. / Master of Science

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / Reconfigurable patch antenna integrated with RF mircoelectromechanical system (MEMS) switches is presented in this paper. The proposed antenna radiates circularly polarized wave at selectable dual frequencies (4.7 GHz and 7.5GHz) of high frequency ratio (1.6:1). The switches are incorporated into the diagonally-fed square patch for controlling the operation frequency, and a rectangular stub attached to the edge of the patch acts as the perturbation to produce the circular polarization. Gain of proposed antenna is 5 - 6dBi, and axial ratio satisfies 3dB criterion at both operating frequencies. The switches are monolithically integrated on quartz substrate. The antenna can be used in applications requiring frequency diversity of remarkable high frequency ratio.