Ce travail de thèse porte sur l'intégration de matériaux de haute constante diélectrique (High-k) en tant que diélectrique interpoly dans les mémoires non volatiles de type Flash. L'objectif est de déterminer quel matériaux High-k seraient des candidats probables au remplacement de l'empilement ONO utilisé en tant que diélectrique interpoly. Une gamme de matériaux high-k ont été étudiés via des caractérisations électriques (I-V, C-V, statistique de claquage…) et physiques (TEM, EDX, XPS…) afin d'éliminer les matériaux ne répondant pas au cahier des charges d'un diélectrique interpoly. Les difficultés et les obstacles liés a l'intégration de matériaux High-k dans une chaine de procédés de fabrication de mémoires Flash ont été pris en compte, et des solutions ont été proposées. / The work of this thesis is on integration of high dielectric constant materials (High-k) as dielectric interpoly in Flash non volatile memories. The objective is to determine which High-k materials are suitable as interpoly dielectric in place of the ONO stack currently used. A range of High-k materials have been studied by electrical characterizations (I-V, C-V, breakdown statistics…) and physical characterizations (TEM, EDX, XPS…) in order to select those with the best properties for an interpoly dielectric. The difficulties in integration of High-k materials in a Flash memory process flow have been taken in account and solutions have been proposed.

Le titanate de baryum et de strontium (BaSrTiO3) est un matériau diélectrique de synthèse à forte permittivité possédant la propriété d'être accordable lorsqu'il est soumis à un champ électrique. Ceci est lié à sa structure cristalline à maille perovskite. Son intégration dans des dispositifs capacitifs est donc prometteuse pour l'industrie de la microélectronique. Il est déposé en couches minces par pulvérisation cathodique à partir de cibles pressées à froid au sein du laboratoire. L'étude de la croissance du matériau, dopé ou non, et de ses propriétés électriques à 100 khz ont permis d'envisager une montée en fréquence. Les évolutions de la permittivité diélectrique complexe et de l'accordabilité du matériau ont ainsi pu être étudiées sur un dispositif spécifique dans une gamme de fréquences allant de 1 à 60 ghz. L'utilisation d'un logiciel de simulation numérique par éléments finis (ELFI) dans le cadre de l'étude à haute fréquence permet de remonter aux caractéristiques propres du matériau, et ainsi d'interpréter plus finement les résultats issus de l'étude en basse fréquence. L'ensemble des connaissances acquises permet finalement de développer des dispositifs à capacité variable qui sont actuellement en cours d'élaboration au sein du laboratoire. / The barium and strontium titanate (BST) is a human made dielectric material with a high dielectric constant which is tunable once submitted to an electric field. This is due to its crystalline structure based on a perovkite mesh. Its integration into capacitive devices is thus fully promising for microelectronic industry. The material is deposited by RF magnetron sputtering from cold pressed targets made in the laboratory. Studying the growth of the material, doped or not, and its electrical properties at 100 kHz has allowed increasing frequency. The variations of the complex permittivity and tunability have thus been studied on a range of frequencies from 1 to 60 GHz. Using the numerical simulation software Elfi enables one to get a good estimation of the intrinsic properties of BST and a sharper explanation of the results obtained at low frequencies. This knowledge finally allows engineering in varactor devices, which is now in progress.

Les systèmes d’information actuels reposent fortement sur les technologies micro-ondes utilisées pour les communications hertziennes. L’amélioration des performances des MEMS radio fréquence aptes à fonctionner dans la bande X (8 GHz et 12 GHz) est un enjeu important pour des applications de télécommunications mais aussi pour les applications radar. Pour y parvenir l’intégration de matériaux ferroélectriques à haute constante diélectrique est requise. Les matériaux qui possèdent de telles propriétés et qui sont les plus adaptés, sont les composés qui dérivent de la structure pérovskite. Intégrer ce type de matériaux dans des commutateurs radio-fréquence (MEMS-RF) pose de nouveaux chalenges en termes de maîtrise du matériau et de compatibilité avec les technologies MEMS existantes. Cette thèse s’est portée sur le composé PMN-PT avec la composition 65/35 qui possède une permittivité relative supérieure à 10000 sous forme de matériau massif.Ce travail de thèse a été consacré à l’étude de l’intégration du composé PMN-PT dans des composants passifs que sont les commutateurs MEMS. Dans la gamme de fréquence d’intérêt, de 500 MHz jusqu’à 20 GHz, les propriétés de ces matériaux ont été peu étudiées sur les matériaux massifs et encore moins sous forme de films minces. L’objectif de cette thèse était de réaliser les couches minces ferroélectriques et de tester leur compatibilité dans l’ensemble du fonctionnement d’un composant MEMS mais aussi de mener une étude réciproque : l’analyse des FeMEMS (MEMS basé sur les ferroélectriques) permettant de compléter les connaissances de ces matériaux dans cette gamme de fréquence. Ce travail est d’intérêt pour l’industrie de la technologie MEMS mais aussi pour la science des matériaux ferroélectriques mais aussi par la compréhension des mécanismes physiques gouvernant aux propriétés diélectriques en termes de pertes notamment dans ce domaine de fréquences.Les caractérisations des MEMS-RF présentées dans cette thèse ont démontré la compatibilité du MEMS PMN-PT dans la gamme de fréquence entre 500MHz et 10 GHz avec de très bonnes performances. En utilisant cette adaptation, la technologie actuelle est ainsi capable de couvrir tous les bandes de fréquence les plus importantes : la bande de télécommunication civile de 1 GHz à 5 GHz en utilisant le PMN-PT, la bande X pour les satellites entre 5 GHz et 15 GHz avec PZT et la bande de haute fréquence de 15 GHz à 40 GHz pour la défense avec les diélectriques traditionnels (Si3N4). / The current information systems depend strongly on the microwave technology used for wireless communications. The enhanced performance of MEMS radio frequency capacity in X-band (8 GHz and 12 GHz) is an important issue not only for Telecom applications but also for Radar applications. The integration of ferroelectric materials with high-k t is highly demanded to replace the traditional dielectrics. This high-k property is accessible for compounds derived from the perovskite structure. Incorporating such materials in switches radio-frequency (RF-MEMS) impose however new chalenges in terms of the compatibility with the existing MEMS technologies. This thesis is focused on the compound PMN-PT with composition 65/35, which has a relative permittivity greater than 10,000 in the form of bulk material.This thesis has been devoted to the study of the integration of PMN-PT thin films in passive components such as MEMS switches. In the frequency range of interest, 500 MHz to 20 GHz, the properties of these materials have not been studied in bulk materials and even less in the form of thin films. The aim of this thesis was to fabricate the ferroelectric thin films and test their compatibility in the overall operation of a MEMS component. This study provides a reciprocal analysis FeMEMS (MEMS based on ferroelectrics) to complete knowledge of these materials in this frequency range. This work makes interest to both the industry and MEMS ferroelectric materials science who is trying to understand the physical mechanisms governing the dielectric properties in terms of losses in this particular range of frequencies.The characterizations of RF-MEMS presented in this thesis have demonstrated the compatibility of MEMS PMN-PT in the frequency range between 500MHz to 10 GHz with very good performance. Using this adaptation, the current technology is able to cover the most important frequency bands: the civil band telecommunication 1 GHz to 5 GHz using the PMN-PT, the X-band satellites between 5 GHz and 15 GHz with PZT and high frequency band of 15 GHz to 40 GHz for the defense with traditional dielectric (Si3N4).

Dans le domaine des Lab-on-a-chip (LOC), la géométrie des canaux d'une puce microfluidique est souvent spécifique à la réalisation d'un protocole donné. La géométrie d'une puce est définie à l'étape de conception, avant les étapes de fabrication (généralement longues et coûteuses), et ne peut être modifiée a posteriori. Ce constat devient problématique lorsque la géométrie ne répond pas de façon satisfaisante au cahier des charges et qu'un nouveau lot de fabrication doit être démarré afin de redimensionner la puce. Pour pallier cet inconvénient, nous proposons de développer des puces microfluidiques génériques dont la géométrie est programmable et reconfigurable. Ce concept s'appuie largement sur les deux techniques de microfluidique digitale, l'électromouillage sur diélectrique (EWOD) et la diélectrophorèse liquide (LDEP). La première voie d'étude se concentre sur la technique de microfluidique LDEP. Tout d'abord, un modèle électromécanique, décrivant les comportements des liquides lors d'actionnements par LDEP ou EWOD, est établi. Ce modèle sert ensuite de base pour la conception et la fabrication de designs LDEP. Ces derniers sont testés afin d'identifier les géométries et les empilements technologiques, offrant des actionnements LDEP optimisés. L'étude, qui prend en compte un grand nombre de paramètres, montre que, avec des configurations et conditions spécifiques, les actionnements de liquide par LDEP offrent des performances égales, a minima, sur certains points, et supérieures sur d'autres par rapport à l'ensemble des études reportées dans la littérature. Enfin, un protocole de fonctionnalisation de surface par des spots de polymère de quelques microns à plusieurs dizaines de microns de diamètre, utilisant la technologie LDEP, est décrit. Cette méthode est susceptible de concurrencer directement les méthodes de fonctionnalisation classiques. La seconde voie d'étude traite du concept de géométrie programmable et reconfigurable, à l'aide de plateformes microfluidiques couplant les effets LDEP et EWOD. Dans un premier temps, les plateformes en configuration " ouverte " permettent de produire des moules à géométrie programmable pour la réalisation de puces microfluidiques en PDMS. Les résultats de cette étude prometteuse aboutissent, entre autres, à la réalisation de géométries de canaux complexes et typiques dans le domaine de la microfluidique (jonctions en " T " et valves de type " Quake "). Dans un second temps, les résultats les plus aboutis de ce manuscrit sont exposés à propos du concept de géométrie programmable et reconfigurable en utilisant de la paraffine. Un protocole spécifique, exploitant judicieusement les déplacements de liquides par EWOD et LDEP, donne lieu à la fabrication d'un grand nombre de puces microfluidiques, comportant des géométries de canaux complexes et variées. Dans les deux cas, un grand nombre de géométries peut être généré a à partir d'une seule plateforme microfluidique digitale générique. Les résultats obtenus ouvrent des perspectives de travail originales et prometteuses, dont certaines d'entre elles sont abordées en marge des objectifs initiaux. La première se trouve dans la continuité du concept de géométrie programmable et reconfigurable, en proposant une technologie à bas coût (substrat souple en Kapton et impression d'électrodes avec de l'encre conductrice). La seconde perspective instruit la compatibilité des technologies comportant des structures résonantes de type MEMS et des structures métalliques LDEP (en polysilicium) à l'échelle submicronique. / In the field of lab-on-a-chip (LOC) systems, the channel geometry of a microfluidic chip is often specific to perform a given protocol. The chip geometry is hence defined at the design step, before the fabrication steps (generally time consuming and expensive) and cannot be thereafter modified. This fact becomes an issue when the geometry does not fit satisfactorily to the specifications and a new batch of fabrication has to be started, to size afresh the microfluidic chip. To overcome this inconvenient we propose to develop a new generation of microfluidic chips with a programmable and reconfigurable geometry. This concept is widely based on both digital microfluidic techniques, the electrowetting on dielectrics (EWOD) and the liquid dielectrophoresis (LDEP) actuations. The first investigation is focused on the microfluidic technique LDEP. First, an electromechanical model for liquids behaviours during a EWOD or LDEP actuation is established. This model is then used as a basis for the LDEP patterns design and fabrication. The LDEP patterns are tested to identify the geometries and dielectric layers stacks which give optimized LDEP actuations. By taking into account a broad parameters range, the study shows that, within a precise setup and specific conditions, the LDEP actuations can have equal performances at the minimum, or better performances than those reported in the overall scientific literature until now. Finally, a surface functionalization protocol by polymer spots (diameter size ranging from a few microns to several dozens of microns) utilizing the LDEP technology is described. This method is likely to compete directly with the standard functionalization tools. The second investigation is dealing with the programmable and reconfigurable geometry concept, thanks to microfluidic platforms which get together both EWOD and LDEP technologies on a same component. Firstly, the microfluidic platform in a single plate configuration allows providing master molds with a programmable geometry for the PDMS microfluidic chip fabrication. The results about this promising study lead to the processing of complex channels geometries, typically used in the microfluidic field. Secondly, the more exciting results are exposed about the programmable and reconfigurable microfluidic concept, by using advantageously the paraffin material. A specific protocol which takes advantages of LDEP and EWOD liquids displacements produces a lot of various and different microfluidic chips with complex channels shapes. For both applications, a single generic microfluidic platform can generate a wide number of different geometries, which can be modified partially or totally thereafter. The obtained results open up novel and promising work prospects, which one of them are approached on the fringe of the initial purposes. The first one belongs to the continuity of the programmable and reconfigurable by suggesting a low cost technology based on flexible Kapton substrate and inkjet printing of silver nanoparticules. The second one investigates the technologies compatibility between MEMS/NEMS resonating structures and LDEP metal structures (in polysilicon) at the submicronic scale.

Recently, high-κ materials have become the focus of research and been extensively utilized as the gate dielectric layer in aggressive scaled complementary metal-oxide-semiconductor (CMOS) technology. Hafnium dioxide (HfO2) is the most promising high-κ material because of its excellent chemical, thermal, mechanical and dielectric properties and also possesses good thermodynamic stability and better band offsets with silicon. Hence, HfO2 has already been used as gate dielectric in modern CMOS devices. For future technologies, it is very difficult to scale the silicon transistor gate length, so it is a necessary requirement of replacing the channel material from silicon to some high mobility material. Two-dimensional layered materials such as graphene and molybdenum disulfide (MoS2) are potential candidates to replace silicon. Due to its planar structure and atomically thin nature, they suit well with the conventional MOSFET technology and are very stable mechanically as well as chemically. HfO2 plays a vital role as a gate dielectric, not only in silicon CMOS technology but also in future nano-electronic devices such as graphene/MoS2 based devices, since high-κ media is expected to screen the charged impurities located in the vicinity of channel material, which results in enhancement of carrier mobility. So, for sustenance and enhancement of new technology, extensive study of the functional materials and its processing is required. In the present work, optimization of HfO2 thin films for gate dielectric applications in Nano-electronic devices using electron beam evaporation is discussed. HfO2 thin films have been optimized in two different thickness regimes, (i) about 35 nm physical thicknesses for back gate oxide graphene/MoS2 transistors and (ii) about 5 nm physical thickness to get Equivalent Oxide Thickness (EOT) less than 1 nm for top gate applications. Optical, chemical, compositional, structural and electrical characterizations of these films have been done using Ellipsometry, X-ray Photoelectron Spectroscopy (XPS), Rutherford Back Scattering (RBS), X-ray Diffraction (XRD), Capacitance-Voltage and Current-Voltage characterization techniques. The amount of O2 flow rate, during evaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post deposition annealing (PDA) and post metallization annealing (PMA) in forming gas ambient (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O2 flow rate shows the best properties as measured on MOS capacitors. A high density film (ρ=8.2 gram/cm3, 85% of bulk density) with high dielectric constant of κ=19 and leakage current density of J=2.0×10-6 A/cm2 at -1 MV/cm has been achieved at optimized deposition conditions. Bilayer graphene on HfO2/Si substrate has been successfully identified and also transistor has been fabricated with HfO2 (35 nm) as a back gate. High transconductance compared to other back gated devices such as SiO2/Si and Al2O3/Si and high mobility have been achieved. The performance of back gated bilayer graphene transistors on HfO2 films deposited at two O2 flow rates of 3 SCCM and 20 SCCM has been evaluated. It is found that the device on the film deposited at 3 SCCM O2 flow rate shows better properties. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices. MoS2 layers on the optimized HfO2/Si substrate have been successfully identified and transistor has been fabricated with HfO2 (32 nm) as a back gate. The device is switching at lower voltages compared to SiO2 back gated devices with high ION/IOFF ratio (>106). The effect of film thickness on optical, structural, compositional and electrical properties for top gate applications has been studied. Also the effect of gate electrode material and its processing on electrical properties of MOS capacitors have been studied. EOT of 1.2 nm with leakage current density of 1×10-4 A/cm2 at -1V has been achieved.

Metal-insulator-metal (MIM) capacitors are used for analog, RF, and DRAM applications in ICs. The International Technology Roadmap for Semiconductors (ITRS) specifies continuing increase in capacitance density (> 7 fF/ m2), lower leakage current density (< 10 8 A/cm2), very low effective oxide thickness (EOT < 1 nm, for DRAM applications), and better capacitance density-voltage (C-V) linearity ( < 100 ppm/V2, for analog/RF applications). In addition, the maximum fabrication/processing temper-ature should not be greater than 400 0C, in order to be compatible with the thermal budget of back-end fabrication steps. Low dielectric constants of conventional SiO2 and Si3N4 capacitors limit the capacitance densities of these devices. Although scaling down of dielectric thickness increases the capacitance density, it results in large leakage current density and poor C-V linearity. In this work, the effects of high-k materials (Eu2O3, Gd2O3, TiO2) on the device performance of MIM capacitors are studied. The performance of multi-dielectric stack, and doped-dielectric stack devices are also investigated. The effects of anneal temperature, anneal ambient, anneal mode, and dielectric thickness on device performance are evaluated. C-V, current density-voltage (J-V), and reliability measurements are performed to benchmark the electrical performance, and this is correlated to the structural and material properties of the films through ellipsometry, scanning electron microscopy (SEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS) measurements. High-performance MIM capacitors are fabricated by using (RF sputtered) Eu2O3 dielectric. The fabricated devices are subjected to different anneal conditions, to study their device performance. Forming gas (FG) and argon (Ar) annealed devices are shown to have higher capacitance densities (7 fF/ m2jF G), lower leakage current densities (3.2 10 8 A/cm2jAr at -1 V), and higher , compared to oxygen (O2) annealed de-vices ( 100kHz = 193 ppm/V2jO2). The electrical characterization results are correlated with the surface chemical states of the films through XPS measurements. The annealing ambient is shown to alter the surface chemical states, which, in turn, modulate the electrical characteristics. High-density MIM capacitors are fabricated by using (RF sputtered) Gd2O3, and Gd2O3-Eu2O3 stacked dielectrics. The fabricated Gd2O3 capacitors are also subjected to different anneal conditions, to study their device performance. Although Gd2O3 capacitors provide high capacitance density (15 fF/ m2), they suffer from high leakage current density, high , and poor reliability. Therefore, stacked dielectrics of Gd2O3 and Eu2O3 (Gd2O3/Eu2O3 and Eu2O3/Gd2O3) are fabricated to reduce leakage current density, improve , and improve reliability, with only a marginal reduction in capacitance density, compared to Gd2O3 capacitors. Density of defects and barrier/trap heights are extracted for the fabricated capacitors, and correlated with the device characteristics. High-performance MIM capacitors with bilayer dielectric stacks of (ALD-deposited) TiO2-ZrO2, and Si-doped ZrO2 are characterized. Devices with (ALD-deposited) TiO2/ ZrO2/TiO2 (TZT) and AlO-doped TZT stacks are also characterized. The influence of doping on the device performance is studied. The surface chemical states of the deposited films are analyzed by high-resolution XPS. The structural analysis of the samples is performed by XRD measurements, and this is correlated to the electrical characteristics of the devices. Reliability measurements are performed to study the effects of constant voltage and current stress on device performance. High capacitance density (> 45 fF/ m2), low leakage current density (< 5 10 8 A/cm2 at -1 V, for most devices), and sub-nm EOT are achieved. These parameters exceed the ITRS specifications for DRAM storage capacitors.