GaN holds significant potential as a material for vertical p-n diodes, enabling the realization of devices with reverse breakdown voltages of 5 kV or higher. Carbon serves as the primary compensating dopant in the growth process, incorporated into GaN during metalorganic chemical vapor deposition (MOCVD) growth. The level of carbon incorporation depends on several factors, including growth rate, ammonia flow, temperature, pressure, and trimethylgallium (TMGa) flow. Through guided empirical modeling, it was demonstrated that the carbon incorporation in GaN growth could be predicted using a single parameter based on the ratio of ammonia flow to the growth rate. This model accurately predicts carbon concentrations ranging from 1x1017 to 5x1014 cm-3 while allowing for maximized growth rates. Other extrinsic dopants have either been reduced below the threshold of consideration or modeled using similar single-parameter relationships. By identifying the dominant extrinsic dopants and accounting for them, an intrinsic defect with a concentration of 2.2x1015 cm-3 was identified. By combining these relationships, growth conditions for n-GaN were optimized, resulting in electron concentrations as low as 1x1015 cm-3. Leveraging these techniques, p-n diodes were grown, achieving a reverse breakdown voltage as high as 3.1 kV. / Doctor of Philosophy / Power electronic devices based on vertical GaN have the potential to revolutionize applications such as electric vehicles, solar charging systems, and the smart grid. However, there are significant materials challenges that need to be addressed in order to realize these devices. They must be extremely pure and extremely thick. Unfortunately, the primary source of these materials also contains carbon, which can negatively impact purity. To overcome this challenge, an empirical model for the growth process has been developed. This model enables independent control over the carbon source and the removal of carbon, using a single parameter. By leveraging this model, it becomes possible to optimize the trade-off between high purity, high growth rates, and ideal electronic properties. Using these techniques, devices were grown with next-generation levels of performance at minimal time and cost.

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<p>InP nanowires with short InAs segments were grown on InP (111)B substrates by Au assisted vapour-liquid-solid growth in a gas source molecular beam epitaxy system. Nanowire crystal structure and morphology were investigated by transmission electron microscopy as a function of temperature, growth rate, and V/III flux ratio. At 370C predominantly kinked nanowires with random morphology and low areal density were observed with a rough parasitic 2D film. At 440C, nanowire density was also reduced but the 2D film growth was smoother and nanowires grew straight without kinking. An optimum temperature of 400C maximized areal density with uniform nanowire morphology. At the optimum temperature of 400C, an increase in V/III flux ratio changed the nanowire morphology from rod-shaped to pencil like indicating increased radial growth. Growth rate did not affect the crystal structure of InP nanowires. For InAs nanowires, changing the growth rate from 1 to 0.5 μm/hr reduced the presence of stacking faults to as low as one per nanowire. Short InAs segments in InP nanowires were found to grow through two mechanisms for nanowires of length L and diameter D. The first mechanism described the supply of In to the growth front via purging of In from the Au droplet where L was proportional to D. The second mechanism involved direct deposition of adatoms on the nanowire sidewall and subsequent diffusion to the growth front where L was proportional to 1/D. For intermediate growth durations, a transition between these two mechanisms was observed. For InP and InAs nanowires, the growth mode was varied from axial to radial through the inclusion of Al to form a core shell structure. Al_xIn_1-xAs(P) shells were grown on InAs cores with Al alloy fractions between 0.53 and 0.2. These nanowires were examined by transmission electron microscopy and it was found, for all values of x in InAs-Al_xIn_1-xP structures, that relaxation had occurred through the introduction of dislocations. For InAs-Al_xIn_1-xAs structures, all values except x=0.2 had relaxed through dislocation formation. A critical thickness model was developed to determine the core-shell coherency limits which confirmed the experimental observation of strain relaxation. The effects of passivation on the electronic transport and the optical properties were examined as a function of structural core-shell passivation and chemical passivation. The mechanisms for the observed improvement in mobility for core-shell versus bare InAs nanowires was due to the reduction in ionized impurity scattering from surface states. Similarly an increase in photoluminescence intensity after ammonium sulfide passivation was explained by the reduction of donor type surface states.</p> / Doctor of Philosophy (PhD)

<p>An ammonium polysulfide (NH₄)₂S_x solution was optimized through a series of experiments to be used for surface passivation of III-V nanowires . The effectiveness of sulfur passivation was investigated by measuring the photoluminescence from p-InP nanowires before and after passivation. The optimized parameters included solvent type, molarity and passivation time. According to the experiments, passivation of nanowires in 0.5 M solution diluted in isopropyl alcohol for 5 min produced the maximum photoluminescence improvement. It was also demonstrated that the whole surface passivation of vertical nanowires in ensemble samples caused a 40 times increase in the photoluminescence intensity while top surface passivation of individual nanowires resulted in a 20 times increase of photoluminescence intensity. A model was developed to calculate the photoluminescence from single nanowires under different surface recombination and surface potential. The model showed that the 40 times increase in the photoluminescence is mainly due to the reduction of surface state density from 10¹² cm^-2before passivation to 5×10¹⁰ cm^-2after passivation.</p> <p>The effect of sulfur passivation on core-shell p-n junction GaAs nanowire solar cells has been investigated. The relative cell efficiency increased by 19% after passivation.</p> / Doctor of Philosophy (PhD)

The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion smart devices will be connected and online by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications. / Ph. D.

Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing total power consumption and thus, necessitates supply voltage scaling in order to maintain low-power device operation. However, with increased supply voltage scaling, transistor drive current is significantly degraded due to the low carrier mobility of Si. To overcome the key challenges of device and voltage scaling required for low-power electronic operation without the degradation of transistor drive current requires the adoption of narrow bandgap channel materials with superior transport properties. However, the use of such materials as bulk substrates remains cost-prohibitive. Thus, another key challenge lies in the heterogeneous integration of high-mobility channel materials on affordable, established Si platform. Germanium (Ge) is an attractive candidate for next-generation low-power devices owing to its high electron and high hole mobility. Recently, AlAs/GaAs epilayers were demonstrated as a potential buffer platform for next-generation Ge-based electronics integrated on Si substrate. This research systematically investigates the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C's) fabricated on the aforementioned stack. Further passivation techniques and interface engineering is then pursued on MOS-C's fabricated from (100) and (110) crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks, balancing out effective oxide thickness (EOT) and reduction of oxide and interfacial traps in order to ensure a pristine interfacial quality for high-performance electronic applications. Further, work function tuning is demonstrated for the first time on the different crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks using two different gate metals, demonstrating the tunability of threshold voltage, VTH, required for transistor applications. The research demonstrates the feasibility of future high-mobility channel material integration on Si via large bandgap buffer architectures for high-speed, low-power, high-performance CMOS logic applications. / Master of Science