Ce mémoire utilise les trois panels de l'Enquête sur la dynamique de travail et du revenu (EDTR) pour évaluer la façon dont s'intègrent les immigrants dans le marché du travail canadien. L'analyse se penche sur deux méthodes économétriques différentes soit l'analyse utilisant des coupes transversales qui a été utilisée dans plusieurs recherches antérieures et l'analyse utilisant des données longitudinales, ce qui permet de voir l'évolution dans le temps des différents travailleurs de l'échantillon. Nous cherchons à mesurer le rendement des différents facteurs que nous retrouvons dans la théorie du capital humain, les effets existant selon la province de résidence du travailleur et la différence selon le sexe des travailleurs par rapport au salaire horaire réel de travail, au heures de travail annuelles rémunérées et au revenu de travail réel annuel. Nous comparons les résultats obtenus pour les immigrants et les travailleurs d'origine canadienne. Les résultats démontrent qu'il y a des provinces où l'intégration des immigrants est plus efficace que dans d'autres. Dans l'ensemble, les critères utilisés par le gouvernement canadien pour accueillir les nouveaux immigrants sont efficaces. Toutefois, nous notons des différences, parfois importantes, avec les travailleurs d'origine canadienne.

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay.

Transposable elements (TEs) are utilized for the creation of a wide range of transgenic organisms. However, in some systems, this technique is not very efficient due to low transposition frequencies and integration into unstable or transcriptionally inactive genomic regions. One approach to ameliorate this problem is to increase knowledge of how transposons move and where they integrate into target genomes. Most transposons do not insert randomly into their host genome, with class II TEs utilizing target sequences of between 2 – 8 bp in length, which are duplicated upon insertion. Furthermore, amongst insertion sites, certain sites are preferred for insertion and hence are classified as hot spots, while others not targeted by TEs are referred to as cold spots. The hypothesis tested in this analysis is that in addition to the primary consensus target sequence, secondary and tertiary DNA structures have a significant influence on TE target site preference. Bioinformatics was used to predict and analyze the structure of the flanking DNA around known insertion sites and cold spots for various TEs, to understand why insertion sites are used preferentially to cold spots for element integration. Hidden Markov Models were modeled and trained to analyze datasets of insertions of the P element in the Drosophila melanogaster genome, the Tc1 element in the Caenorhabditis elegans genome, and insertions of the Mos1, piggyBac and Hermes transposons into the target plasmid pGDV1. Analysis of the DNA structural profiles of the insertion sites for the P element and Hermes transposons revealed that both transposons targeted regions of DNA with a relatively high degree of bendability/flexibility at the insertion site. However, similar trends were not observed for the Tc1, Mos1 or piggyBac transposons. Hence, it is believed that the secondary structural features of DNA can contribute to target site preference for some, but not all transposable elements.

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are presented for the procedure of performance and power optimization. The second chapter focuses on improving circuit performance under inductance effect. The new algorithm works under the dynamic programming framework and runs in provably linear time for multiple buffer types due to two novel techniques: restrictive cost bucketing and efficient delay update. The experimental results demonstrate that our linear time algorithm consistently outperforms all known RLC buffering algorithms in terms of both solution quality and runtime. That is, the new algorithm uses fewer buffers, runs in shorter time and the buffered tree has better timing. The third chapter presents a method to guarantee a high fidelity signal transmission in global bus. It proposes a new redundant via insertion technique to reduce via variation and signal distortion in twisted differential line. In addition, a new buffer insertion technique is proposed to synchronize the transmitted signals, thus further improving the effectiveness of the twisted differential line. Experimental results demonstrate a 6GHz signal can be transmitted with high fidelity using the new approaches. In contrast, only a 100MHz signal can be reliably transmitted using a single-end bus with power/ground shielding. Compared to conventional twisted differential line structure, our new techniques can reduce the magnitude of noise by 45% as witnessed in our simulation. The fourth chapter proposes a buffer insertion and gate sizing algorithm for million plus gates. The algorithm takes a combinational circuit as input instead of individual nets and greatly reduces the buffer and gate cost of the entire circuit. The algorithm has two main features: 1) A circuit partition technique based on the criticality of the primary inputs, which provides the scalability for the algorithm, and 2) A linear programming formulation of non-linear delay versus cost tradeoff, which formulates the simultaneous buffer insertion and gate sizing into linear programming problem. Experimental results on ISCAS85 circuits show that even without the circuit partition technique, the new algorithm achieves 17X speedup compared with path based algorithm. In the meantime, the new algorithm saves 16.0% buffer cost, 4.9% gate cost, 5.8% total cost and results in less circuit delay.

Thèse de doctorat : Sciences de l'éducation : Strasbourg 1 : 2008. / Titre provenant de l'écran-titre. Bibliogr. p. 256-258.

Typescript. / Thesis (Ph. D.)--University of Hawaii at Manoa, 1990. / Includes bibliographical references (leaves 100-109) / Microfiche. / viii, 109 leaves, bound ill. 29 cm

Introduction of new into an existing condition stimulates a dialogue between the two. The new and the existing are juxtaposed. The new structure penetrates into the existing structure. These INSERTIONS are the nexus which connects the new and the existing. The intersections of the new and the existing are the crucial junctions which are explored throughout the process. The insertions are made with a creating a space around it, the VOID which bridges the two eras but retains their distinct characteristics through CONTRASTS. / Master of Architecture

Ce mémoire s'intéresse à la problématique de l'insertion socioprofessionnelle des personnes en situation de handicap en Estrie et vise à comprendre, les enjeux reliés à la dynamique partenariale et au développement local. L'insertion fait appel à différentes stratégies dont la mobilisation efficiente des ressources humaines, matérielles et financières au sein des territoires d'intervention en vue d'atteindre différents objectifs dont l'autonomie et la pleine participation. Cependant cette tendance n'est pas réellement généralisée, même si, désormais elle constitue un défi dans un monde marqué par le contexte de la mondialisation, où l'implication des populations de base, des communautés et des acteurs locaux dans de nouveaux modèles de développement et l'adoption de nouvelles pratiques sociales et économiques, s'avère plus que nécessaire. Généralement dans le cadre des stratégies d'intégration des personnes en situation de handicap, il est souvent difficile de cerner la place réelle accordée au partenariat et au développement local, qu'il s'agisse des planifications ou de l'application concrète des programmes régionaux ou nationaux. Ainsi, à partir d'une démarche inductive de recherche qualitative en sciences sociales, nous avons mené une enquête qui nous a permis de comprendre que la dynamique partenariale dans le cadre de l'insertion socioprofessionnelle des personnes en situation de handicap se manifeste en Estrie principalement par l'existence d'une table de concertation dénommée comité régional pour l'intégration au travail des personnes handicapées (CRITPH) et qui regroupe divers acteurs de différents secteurs qui se concertent de façon périodique autour de la question reliée à la problématique de l'emploi des personnes en situation de handicap. Cette concertation qui met en lien les différents acteurs de la région, a favorisé et maintenu une dynamique partenariale à l'échelle de la région estrienne, et plus particulièrement sur le territoire de la ville de Sherbrooke. Ceci a favorisé la réalisation d'actions communes ayant abouti à la conception et au développement de projets locaux qui s'inscrivent progressivement dans le champ du développement local et dont l'exemple le plus probant ressorti au terme de notre recherche, est communément appelé le projet Rona.

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