Les travaux de cette thèse se concentrent sur la réduction de l'énergie consommée et l'amélioration des temps de réveil du microcontrôleur par des innovations au niveau de l'architecture, du circuit et de la gestion de l'énergie. Ces travaux proposent une architecture de microcontrôleur partitionnée entre un processeur de réveil programmable, appelé Wake Up Controller, s'occupant des tâches courantes du nœud de capteurs et un processeur principal gérant les tâches irrégulières. Le Wake Up Controller proposé dans ces travaux de thèse est un processeur RISC 16-bit dont le jeu d'instructions a été adapté pour gérer les tâches régulières du nœud, et n'exécute que du code sur interruptions. Il est implémenté en logique mixte asynchrone/synchrone. Un circuit a été fabriqué en technologie UTBB FDSOI 28nm intégrant le Wake-Up Controller. Le cœur atteint une performance de 11,9 MIPS pour 125μW de consommation moyenne en phase active et un réveil depuis le mode de veille en 55ns pour huit sources de réveil possibles. La consommation statique est d'environ 4μW pour le cœur logique asynchrone à 0,6V sans utilisation de gestion d'alimentation (power gating) et d'environ 500nW avec. / This PhD work focuses on the reduction of energy consumption and wake up time reduction of a WSN node microcontroller through innovations at architectural, circuit and power management level. This work proposes a partitioned microcontroller architecture between a programmable wake up processor, named Wake Up Controller on which this work is focused, and a main processor. The first deals with the common tasks of a wireless sensor node while the second manages the irregular tasks. TheWake Up Controller proposed in this work is a 16-bit RISC processor whose instruction set has been adapted to handle regular tasks of a sensor node. It only executes code on interruptions. It is implemented in asynchronous / synchronous mixed logic to improve wake up time and energy. A circuit was fabricated in a 28nm UTBB FDSOI technology integrating the Wake Up Controller. The core reaches 11,9 MIPS for 125 μW average power consumption in active phase and wakes up from sleep mode in 55ns from eight possible interruption sources. The static power consumption is around 4μW for the asynchronous logic core at 0.6V without power gating and 500nW when gated.

This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.

Application specific instruction set processors become part of every day life although it's not always visible at first sight. During their development it's needed to somehow describe their architecture, instruction set and behavior. To make their developement worth, it's necessary to be able to create applications for these processors and during application development errors are always made. Debuggers serve to discover and help fixing them. This paper summarises some basic information to debugger development and describes implementation for processors created using the Lissom project.

<p>Computer architecture and assembly language programming microprocessor execution are basic courses taught in every computer science department. Generally, however, students have&nbsp / difficulties in mastering many of the concepts in the courses, particularly students whose first language is not English. In addition to their difficulties in understanding the purpose of given&nbsp / instructions, students struggle to mentally visualize the data movement, control and processing operations. To address this problem, this research proposed a graphical visualization approach&nbsp / and investigated the visual illustrations of such concepts and instruction execution by implementing a graphical visualization simulator as a teaching aid. The graphical simulator developed during the course of this research was applied in a computer architecture course at Kabul University, Afghanistan. Results obtained from student evaluation of the simulator show significant&nbsp / levels of success using the visual simulation teaching aid. The results showed that improved learning was achieved, suggesting that this approach could be useful in other computer science departments in Afghanistan, and elsewhere where similar challenges are experienced.</p>

<p>Computer architecture and assembly language programming microprocessor execution are basic courses taught in every computer science department. Generally, however, students have&nbsp / difficulties in mastering many of the concepts in the courses, particularly students whose first language is not English. In addition to their difficulties in understanding the purpose of given&nbsp / instructions, students struggle to mentally visualize the data movement, control and processing operations. To address this problem, this research proposed a graphical visualization approach&nbsp / and investigated the visual illustrations of such concepts and instruction execution by implementing a graphical visualization simulator as a teaching aid. The graphical simulator developed during the course of this research was applied in a computer architecture course at Kabul University, Afghanistan. Results obtained from student evaluation of the simulator show significant&nbsp / levels of success using the visual simulation teaching aid. The results showed that improved learning was achieved, suggesting that this approach could be useful in other computer science departments in Afghanistan, and elsewhere where similar challenges are experienced.</p>

Made available in DSpace on 2014-12-17T15:48:05Z (GMT). No. of bitstreams: 1 LeonardoAC.pdf: 6046620 bytes, checksum: ad9a9332aa6ef3e81e83f93b75f55894 (MD5) Previous issue date: 2006-05-19 / The Recon&#64257;gurable Computing is an intermediate solution at the resolution of complex problems, making possible to combine the speed of the hardware with the &#64258;exibility of the software. An recon&#64257;gurable architecture possess some goals, among these the increase of performance. The use of recon&#64257;gurable architectures to increase the performance of systems is a well known technology, specially because of the possibility of implementing certain slow algorithms in the current processors directly in hardware. Amongst the various segments that use recon&#64257;gurable architectures the recon&#64257;gurable processors deserve a special mention. These processors combine the functions of a microprocessor with a recon&#64257;gurable logic and can be adapted after the development process. Recon&#64257;gurable Instruction Set Processors (RISP) are a subgroup of the recon&#64257;gurable processors, that have as goal the recon&#64257;guration of the instruction set of the processor, involving issues such formats, operands and operations of the instructions. This work possess as main objective the development of a RISP processor, combining the techniques of con&#64257;guration of the set of executed instructions of the processor during the development, and recon&#64257;guration of itself in execution time. The project and implementation in VHDL of this RISP processor has as intention to prove the applicability and the ef&#64257;ciency of two concepts: to use more than one set of &#64257;xed instructions, with only one set active in a given time, and the possibility to create and combine new instructions, in a way that the processor pass to recognize and use them in real time as if these existed in the &#64257;xed set of instruction. The creation and combination of instructions is made through a recon&#64257;guration unit, incorporated to the processor. This unit allows the user to send custom instructions to the processor, so that later he can use them as if they were &#64257;xed instructions of the processor. In this work can also be found simulations of applications involving &#64257;xed and custom instructions and results of the comparisons between these applications in relation to the consumption of power and the time of execution, which con&#64257;rm the attainment of the goals for which the processor was developed / A Computa??o Recon&#64257;gur?vel ? uma solu??o intermedi?ria na resolu??o de problemas complexos, possibilitando combinar a velocidade do hardware com a &#64258;exibilidade do software. Uma arquitetura recon&#64257;gur?vel possui v?rias metas, entre estas o aumento de desempenho. Dentre os v?rios segmentos em rela??o ?s arquiteturas recon&#64257;gur?veis, destacam-se os Processadores Recon&#64257;gur?veis. Estes processadores combinam as fun??es de um microprocessador com uma l?gica recon&#64257;gur?vel e podem ser adaptados depois do processo de desenvolvimento. Processadores com Conjunto de Instru??es Recon&#64257;gur?veis (RISP -Recon&#64257;gurable Instruction Set Processors) s?o um subconjunto dos processadores recon&#64257;gur?veis, que visa como meta a recon&#64257;gura??o do conjunto de instru??es do processador, envolvendo caracter?sticas referentes aos padr?es de instru??es como formatos, operandos, e opera??es elementares. Este trabalho possui como objetivo principal o desenvolvimento de um processador RISP, combinando as t?cnicas de con&#64257;gura??o do conjunto de instru??es do processador executadas em tempo de desenvolvimento, e de recon&#64257;gura??o do mesmo em tempo de execu??o. O projeto e implementa??o em VHDL deste processador RISP tem como intuito provar a aplicabilidade e a e&#64257;ci?ncia de dois conceitos: utilizar mais de um conjunto de instru??o &#64257;xo, com apenas um ativo em determinado momento, e a possibilidade de criar e combinar novas instru??es, de modo que o processador passe a reconhec?-las e utiliz?-las em tempo real como se estas existissem no conjunto de instru??o &#64257;xo. A cria??o e combina??o de instru??es ? realizada mediante uma unidade de recon&#64257;gura??o incorporada ao processador. Esta unidade permite que o usu?rio possa enviar instru??es customizadas ao processador para que depois possa utiliz?-las como se fossem instru??es &#64257;xas do processador. Neste trabalho tamb?m encontram-se simula??es de aplica??es envolvendo instru??es &#64257;xas e customizadas e resultados das compara??es entre estas aplica??es em rela??o ao consumo de pot?ncia e ao tempo de execu??o que con&#64257;rmam a obten??o das metas para as quais o processador foi desenvolvido

This master's thesis deals with creation of generators of the code for existing virtual platforms QEMU and OVP. This work consist of study of techniques, which are used by virtual machines for their work. Main part of this work is the design of process, which transforms input instruction sets to the code used by these virtual platforms. As the result of this work functional programs, which generate the code for these virtual platforms, was created.

The key task of database systems is to efficiently manage large amounts of data. A high query throughput and a low query latency are essential for the success of a database system. Lately, research focused on exploiting hardware features like superscalar execution units, SIMD, or multiple cores to speed up processing. Apart from these software optimizations for given hardware, even tailor-made processing circuits running on FPGAs are built to run mostly stateless query plans with incredibly high throughput. A similar idea, which was already considered three decades ago, is to build tailor-made hardware like a database processor. Despite their superior performance, such application-specific processors were not considered to be beneficial because general-purpose processors eventually always caught up so that the high development costs did not pay off. In this paper, we show that the development of a database processor is much more feasible nowadays through the availability of customizable processors. We illustrate exemplarily how to create an instruction set extension for set-oriented database rimitives. The resulting application-specific processor provides not only a high performance but it also enables very energy-efficient processing. Our processor requires in various configurations more than 960x less energy than a high-end x86 processor while providing the same performance.

Nowadays, network processors are an integral part of information technology. With the deployment of 5G network ramping up around the world, numerous new devices are going to take advantage of their processing power and programming flexibility. Contemporary information technology providers of today such as Ericsson, spend a great amount of financial resources on licensing deals to use processors with proprietary instruction set architecture designs from companies like Arm holdings. There is a new non-proprietary instruction set architecture technology being developed known as Risc-V. There are many open source processors based on Risc-V architecture, but it is still unclear how well an open-source Risc-V processor performs network packet processing tasks compared to an Arm-based processor. The main purpose of this thesis is to design a test model simulating and evaluating how well an open-source Risc-V processor performs packet processing compared to an Arm Cortex M7 processor. This was done by designing a C code simulating some key packet processing functions processing 50 randomly generated 72 bytes data packets. The following functions were tested: framing, parsing, pattern matching, and classification. The code was ported and executed in both an Arm Cortex M7 processor and an emulated open source Risc-V processor. A working packet processing test code was built, evaluated on an Arm Cortex M7 processor. Three different open-source Risc-V processors were tested, Arianne, SweRV core, and Rocket-chip. The execution time of both cases was analyzed and compared. The execution time of the test code on Arm was 67, 5 ns. Based on the results, it can be argued that open source Risc-V processor tools are not fully reliable yet and ready to be used for packet processing applications. Further evaluation should be performed on this topic, with a more in-depth look at the SweRV core processor, at physical open-source Risc-V hardware instead of emulators. / Nätverksprocessorer är en viktig byggsten av informationsteknik idag. I takt med att 5G nätverk byggs ut runt om i världen, många fler enheter kommer att kunna ta del av deras kraftfulla prestanda och programerings flexibilitet. Informationsteknik företag som Ericsson, spenderarmycket ekonomiska resurser på licenser för att kunna använda proprietära instruktionsuppsättnings arkitektur teknik baserade processorer från ARM holdings. Det är väldigt kostam att fortsätta köpa licenser då dessa arkitekturer är en byggsten till designen av många processorer och andra komponenter. Idag finns det en lovande ny processor instruktionsuppsättnings arkitektur teknik som inte är licensierad så kallad Risc-V. Tack vare Risc-V har många propietära och öppen källkod processor utvecklats idag. Det finns dock väldigt lite information kring hur bra de presterar i nätverksapplikationer är känt idag. Kan en öppen-källkod Risc-V processor utföra nätverks databehandling funktioner lika bra som en proprietär Arm Cortex M7 processor? Huvudsyftet med detta arbete är att bygga en test model som undersöker hur väl en öppen-källkod Risc-V baserad processor utför databehandlings operationer av nätverk datapacket jämfört med en Arm Cortex M7 processor. Detta har utförts genom att ta fram en C programmeringskod som simulerar en mottagning och behandling av 72 bytes datapaket. De följande funktionerna testades, inramning, parsning, mönster matchning och klassificering. Koden kompilerades och testades i både en Arm Cortex M7 processor och 3 olika emulerade öppen källkod Risc-V processorer, Arianne, SweRV core och Rocket-chip. Efter att ha testat några öppen källkod Risc-V processorer och använt test koden i en ArmCortex M7 processor, kan det hävdas att öppen-källkod Risc-V processor verktygen inte är tillräckligt pålitliga än. Denna rapport tyder på att öppen-källkod Risc-V emulatorer och verktygen behöver utvecklas mer för att användas i nätverks applikationer. Det finns ett behov av ytterligare undersökning inom detta ämne i framtiden. Exempelvis, en djupare undersökning av SweRV core processor, eller en öppen-källkod Risc-V byggd hårdvara krävs.

The purpose of this MSc thesis is to create design and implementation of program for translation of x86 binary code to a high-level programming language. There is described PE file format for executables used in MS Windows operating systems in the first part of work. This document contains general information about instruction set IA-32, especially a way of decoding binary code to assembly language. There are described typical program constructions, which are being used in compilers. Design of creation high-level programming language was inspired by existing programming languages. Conclusion is made about advantages and disadvantages of approach used in this thesis.