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Algoritmos e arquiteturas para o desenvolvimento de sistemas computacionais / Algorithms and architectures to the development of computational systemsCarro, Luigi January 1996 (has links)
Este trabalho trata de arquiteturas e algoritmos para o desenvolvimento de sistemas computacionais. Tais sistemas são constituídos de um microprocessador (específico ou comercialmente disponível), de seu conjunto de programas e de um HW dedicado que será utilizado para otimização do sistema. O objetivo principal desta tese é demonstrar que, presentemente, a linha divisória entre HW e SW e cada vez mais tênue, e a transição entre um e outro pode ser feita de maneira suave pelo projetista de sistemas, na busca de um ponto ótimo no balanço entre custo e desempenho. Apresenta-se em seqüência o ambiente de CAD, a classificação de rotinas e os métodos de otimização tendo em vista esta classificação para o aumento de desempenho de sistemas computacionais. A seguir são apresentadas técnicas para processadores dedicados de arquitetura Risc, visando a otimização de certos tipos de programas. Os resultados de aceleração são apresentados para um conjunto de exemplos. Tendo em vista o mercado nacional de eletrônica, fortemente baseado em microcontroladores, estudam-se e mostram-se possibilidades de otimização e integração de sistemas baseados em tais processadores, assim como a aplicabilidade das mesmas técnicas para processadores dedicados. A viabilidade técnica desta realização é discutida através de exemplos baseados em aplicações reais. Finalmente, a validação de sistemas computacionais, em especial aqueles trabalhados nesta tese, é discutida. / This work discusses architectures and algorithms for the development of computational systems, which are based on a microprocessor (custom or off-the-shelf), the set of application programs and a dedicated HW, used to increase the performance of the whole system. The goal of this work is to show that, nowadays, the division line between SW and HW is smooth, and the transition from one to the other can be achieved by the system designer using a specific CAD in order to obtain a trade-off between cost and performance. The CAD environment is presented, followed by routine classification and optimization methods based on the former classification to increase the performance of the system. Techniques devoted to systems based on dedicated Risc processors are showed next, to optimize certain type of programs. Positive results are shown for a set of examples. Since the Brazilian electronics market is strongly based on microcontrollers, the study and results of optimization techniques regarding this type of systems are also presented. The same techniques can be applied to dedicated processors as well. Results of this proposal are obtained for a set of real world examples. The last topic of this work regards the validation of computational systems, mainly those presented throughout this work.
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Statistical Design For Yield And Variability Optimization Of Analog Integrated CircuitsNalluri, Suresh Babu 12 1900 (has links) (PDF)
No description available.
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Architectural Synthesis Techniques for Design of Correct and Secure ICsSundaresan, Vijay January 2008 (has links)
No description available.
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Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensorsLevski, Deyan January 2018 (has links)
This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few remaining speed bottlenecks in conventional 2D imagers. At the same time, as pixel dark current continues to improve, the resolution requirements on imaging data converters impose very high system-level design challenges. The focus of the presented investigations here is to shed light on methods in Time-to-Digital Converter interpolation of single-slope ADCs. By using high-factor time-interpolation, the resolution of single-slope converters can be increased without sacrificing conversion time or power. This work emphasizes on solutions for improvement of multiphase clock interpolation schemes, following an all-digital design paradigm. Presented is a digital calibration scheme which allows a complete elimination of analog clock generation blocks, such as PLL or DLL in Flash TDC-interpolated single-slope converters. To match the multiphase clocks in time-interpolated single-slope ADCs, the latter are generated by a conventional open-loop delay line. In order to correct the process voltage and temperature drift of the delay line, a digital backend calibration has been developed. It is also executed online, in-column, and at the end of each sample conversion. The introduced concept has been tested in silicon, and has showed promising results for its introduction in practical mass-production scenarios. Methods for reference voltage generation in single-slope ADCs have also been looked at. The origins of error and noise phenomenona, which occur during both the discrete and continuous-time conversion phases in a single-slope ADC have been mathematically formalized. A method for practical measurement of noise on the ramp reference voltage has also been presented. Multiphase clock interpolation schemes are difficult for implementation when high interpolation factors are used, due to their quadratic clock phase growth with resolution. To allow high interpolation factors a time-domain binary search concept with error calibration has been introduced. Although the study being conceptual, it shows promising results for highly efficient implementations, if a solution to stable column-level unit delays can be found. The latter is listed as a matter of future investigations.
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Inductorless balun low-noise amplifier (LNA) for RF wideband application to IEEE 802.22 / Um amplificador de baixo ruído banda larga, sem indutor, com alta linearidade e 24 dB de ganho para a banda do padrão IEEE 802.22Costa, Arthur Liraneto Torres January 2014 (has links)
Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V. / A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.
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Inductorless balun low-noise amplifier (LNA) for RF wideband application to IEEE 802.22 / Um amplificador de baixo ruído banda larga, sem indutor, com alta linearidade e 24 dB de ganho para a banda do padrão IEEE 802.22Costa, Arthur Liraneto Torres January 2014 (has links)
Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V. / A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.
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Inductorless balun low-noise amplifier (LNA) for RF wideband application to IEEE 802.22 / Um amplificador de baixo ruído banda larga, sem indutor, com alta linearidade e 24 dB de ganho para a banda do padrão IEEE 802.22Costa, Arthur Liraneto Torres January 2014 (has links)
Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V. / A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.
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Conception orientée délai : étude, développement et réalisation d’une boucle à verrouillage de phase large bande stabilisée par une boucle à verrouillage de délaiLucas de Peslouan, Pierre-Olivier 25 May 2011 (has links)
L’explosion du marché des télécommunications a donné lieu, lors de ces dernières années, à la multiplication des standards de radiocommunication. De nos jours, l’ensemble de ces moyens de communication utilisés pour le transfert de voix et de données doit être intégré dans les terminaux mobiles. Cependant, cette tendance s’oppose aux contraintes de faible coût qui tendent à diminuer la taille de l’électronique embarquée dans un terminal mobile, mais aussi aux contraintes de diminution de la consommation pour une plus grande autonomie des objets sans fils. C’est donc autour de ces verrous technologiques et techniques que se concentre une part importante des efforts de « R&D » aujourd’hui. Ainsi, l’objectif des travaux présentés repose sur la recherche et le développement d'une architecture contribuant à l’amélioration des performances du bloc central de la chaîne d’émission/réception : l'oscillateur local.L’architecture innovante de synthétiseur de fréquence multistandard réalisée est fondée sur le principe de « conception orientée délai » (DOD - Delay Oriented Design). Une nouvelle technique de stabilisation, issue de la superposition d’une boucle à verrouillage de délai et de phase, est proposée afin d’élargir la bande passante.De l’étude système à la mesure en passant par l’étude comportementale et la réalisation du circuit, les différentes étapes de conception de ce système fractionnaire sont présentées. Les simulations et les mesures ont démontré la capacité du synthétiseur à couvrir une bande comprise entre 1,6 et 3,5GHz avec un signal de référence à 500MHz, mais aussi à stabiliser une architecture très large bande. / The explosion of the wireless communication market is largely responsible of the expansion for RF communication standards for voice and data. Nowadays, each one of them must be integrated in one mobile terminal.However, this trend is opposed to the constraints of low cost, which tend to reduce the size of the electronics in a mobile terminal, but also the constraints of reduced consumption for greater autonomy for wireless systems. It is then around these technological and technical barriers that focus an important part of efforts to « R & D » today. Thus, the objective of the work presented is based on research and development of an architecture that contributes to improve the performances of the central block of transceivers: the local oscillator.The innovative architecture of multistandard synthesizer realized is based on the principle of Delay Oriented Design (DOD). A new technique of stabilization, based on the superposition of a delay and a phase locked loop, is proposed to expand the bandwidth. From study system to measurements through the behavioral comportment and implementation of the circuit, the various stages when designing an RF system are presented. Simulations and measurements have demonstrated the ability of the synthesizer to cover a frequency band between 1.6 and 3.5 GHz with a reference signal at 500MHz, but also to stabilize a broadband architecture.
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Entwurf eines ADCs in einer 0.35μm TechnologieKäberlein, Andreas 09 April 2019 (has links)
Die vorliegende Arbeit behandelt den Entwurf eines ADCs nach dem sukzessiven Approximationsverfahren (SAR). Ausgehend von den Systemanforderungen erfolgt eine Ableitung der Spezifikation des zu entwerfenden ADCs. Theoretische Betrachtungen und Highlevelsimulationen in Matlab wählen die optimale Architektur der Einzelkomponenten - kapazitives DAC Array, Komparator, Ablaufsteuerung - aus. Die Implementation selbst findet für die Analogschaltungsteile auf Transistorebene und für die digitalen Komponenten auf RT-Ebene in VHDL statt. Sie bilden die Grundlage für die Realisierung des Layouts. In dem Zusammenhang stellt die Arbeit die gängigsten Matchingmethoden für elektronische Bauelemente vor. Abschließende PEX-Simulationen (parasitic Extraction) ermitteln die statischen (INL/DNL) wie dynamischen Kennwerte (SNR) des SAR-ADCs.:Abkürzungsverzeichnis iii
Formelzeichen v
1 Einleitung 1
2 Grundlagen 2
2.1 Analog/Digital-Umsetzer 2
2.1.1 Umsetzungsverfahren 2
2.1.2 Statische Kennwerte 8
2.1.3 Dynamische Kennwerte 12
2.2 Technologie 17
2.2.1 Übersicht 17
2.2.2 MOS-Transistoren 17
2.2.3 Kapazitäten 18
2.2.4 Widerstände 18
2.3 Hardwarebeschreibungssprache 19
2.3.1 Übersicht 19
2.3.2 Zustandsautomat 19
2.3.3 Look-Ahead-Ausgang 20
3 Spezifikation 21
4 ADU-Topologie 23
4.1 Vorüberlegungen 23
4.1.1 Umsetzungsverfahren 23
4.1.2 Vergleich Widerstand/Kapazität 23
4.1.3 Differenziell Vs. Single-Ended 24
4.1.4 Kapazitätsarray 25
4.2 ADC High-Level Modell 30
4.2.1 Funktionsblöcke 30
4.2.2 Matlab/Simulink 31
4.2.3 Simulation 34
4.3 Parasitäre Effekte 37
4.3.1 Substratkapazität 37
4.3.2 Komparatoroffset 39
5 Schaltungsdesign & -simulation 41
5.1 Komparator 41
5.1.1 Spezifikation 41
5.1.2 Latch 41
5.1.3 Vorverstärker 43
5.1.4 Gesamtsystem 46
5.2 Schalter 46
5.2.1 Funktionsweise 46
5.2.2 Ladungseintrag 46
5.2.3 Dimensionierung & Simulation 47
5.3 Kapazitätsarray 51
5.4 SAR-Controller 51
5.4.1 Vorüberlegung 51
5.4.2 RTL Design 52
5.4.3 Simulation 55
5.4.4 Synthese 57
5.4.5 Optimierung 59
5.5 ADC (Toplevel) 59
5.5.1 Architektur 59
5.5.2 Simulation 61
6 Layout 64
6.1 Komparator 65
6.1.1 Vorverstärker 1 65
6.1.2 Vorverstärker 2 66
6.1.3 Dynamisches Latch 66
6.2 Transmission Gates 67
6.3 Kapazitätsarray 68
6.4 SAR-Controller 70
6.5 ADC (Toplevel) 70
6.6 PEX Simulation 72
6.6.1 Statischer Test 72
6.6.2 Dynamischer Test 73
7 Zusammenfassung 74
Literaturverzeichnis 76
Bücher 76
Skripte und Schriften 76
Internetlinks 78
Abbildungsverzeichnis 79
Tabellenverzeichnis 82
Anhang 84
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Offloading Workloads from CPU of Multiplayer Game Server to FPGA : SmartNIC implementation with UDP Communication / Avlastning av arbetsbelastningar från CPU till FPGA för multiplayer Game Server : SmartNIC-implementering med UDP KommunikationBao, Junwen January 2022 (has links)
For multiplayer games, the performance of the server’s Central Processing Unit (CPU) is the main factor that limits the number of players on the server at the same time. Compared with the CPU, the Field-Programmable Gate Array (FPGA) architecture has no instructions set and no shared memory. Offloading some tasks from the CPU to the FPGA may help the CPU improve processing efficiency. This thesis explores which tasks on a CPU can be offloaded to a FPGA and how to design such a circuit system. The performance of the developed system also needs to be measured. We decided to offload communication tasks and data processing tasks to an FPGA. The result is that the FPGA server is available for work, the maximum number of users is 80, and the maximum network latency is 30-40 ms. The most important result is that a FPGA can be used as a multi-player server. One of the severe limitations of this design is the number of hardware resources. A 7-series FPGA is divided into several similar clock regions, which means the number of Flip Flop (FF)s near the same clock edge is fixed. If adding more FFs in the same component, the routing delay can not meet the set-up time requirements. Previously, people used the FPGA as the support accelerator to the server CPU. The CPU still works as a paramount communication link with one or several multi-connection parts and connects to the FPGA via the Peripheral Component Interconnect Express (PCIe) to use the FPGA to process data or pack/unpack Ethernet frames. We have designed and implemented a whole multi-connection server in a Hardware Description Language (HDL) and downloaded the resulting hardware in an FPGA. / I spel med flera spelare är serverns CPU-prestanda (Central Processing Unit) den viktigaste faktorn som begränsar antalet spelare som servern samtidigt kan hantera. Jämfört med CPU:n har en FPGA (Field-Programmable Gate Array) inga instruktioner och inget delat minne. Avlastning av vissa uppgifter från den CPU till FPGA:n kan hjälpa CPU:n att förbättra bearbetningseffektiviteten. I denna avhandling undersöks vilka uppgifter på en CPU som kan överföras till en FPGA och hur man utformar ett sådant kretsystem. Prestandan hos det utvecklade systemet måste också mätas. Vi har beslutat att avlasta kommunikationsuppgifter och databehandlingsuppgifter. till en FPGA. Resultatet är att FPGA-servern är tillgänglig för arbete, det maximala antalet användare är 80, och den maximala nätverksfördröjningen är 30-40 ms. Det viktigaste resultatet är att en FPGA kan användas som en server för flera spelare. En av de allvarliga begränsningarna med denna konstruktion är antalet hårdvaruresurser. En FPGA i 7-serien är uppdelad i flera liknande klockregioner, vilket innebär att antalet Flip Flop (FF)s nära en klocka är fast. Om man lägger till fler FF:er i samma komponent, kommer fördröjningen inte att uppfylla tidskraven för setup. Tidigare har folk använt sig av FPGA:n som en stödaccelerator till serverprocessorn. CPU:n fungerar fortfarande som en viktig kommunikationslänk med en eller flera anslutningar och ansluter till FPGA:n via Peripheral Component Interconnect Express (PCIe) för att använda FPGA:n till att bearbeta data och paketera/packa upp Ethernet-ramar. Vi har implementerat en hel server med flera anslutningar med hjälp av hårdvaruvarubeskrivande språk (HDL) och laddat ner den resulterande designen i en FPGA.
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