Zur Einsparung von Masse und Volumen fokussiert die Entwicklung automobiler Antriebsstränge eine hohe Integrationsdichte der Komponenten. Bei elektrischen Achsantrieben wird der Trend durch relativ hohe Kosten von Kabeln und Steckern befeuert. Die E-Maschine ist aufgrund ihrer Baugröße in vielen System nur einfach vorhanden, allerdings mit zweigeteilter Wicklung, die im Regelfall jeweils drei Stränge umfasst. Dabei konnten sich Topologien mit Zahnspulenwicklung etablieren, da man sich aufgrund der fehlenden Wickelkopfkreuzungen eine örtliche Isolierung von Wicklungsfehlern verspricht. Eine Fortsetzung des Redundanzprinzips besteht darin, die Anzahl der parallelen Pfade zu erhöhen. Mit jeder Verdopplung der Parallelpfade halbiert sich der Leistungsfluss pro Pfad. Die Folge sind kleinere Leistungshalbleiter und Kühlkörper innerhalb der Stromrichter.

With the increase dependency on electricity to provide correct form of electricity for lightning, machines, and home and office appliances, the need for the introduction of high reliability power electronics in converting the raw form of electricity into efficient electricity for these applications is uprising. One of the most common failures in power electronics is temperature related failure such as overheating. To address the issue of overheating, thermal management becomes an important mission in the design of the power electronics to ensure the functional power electronics. Different approaches are taken by academia and industry researchers to provide efficient power electronics. In particular, the Center for Power Electronics System (CPES) at Virginia Tech and four other universities presented the IPEM approach by introducing integrated power electronics modules (IPEM) as standardized units that will enable greater integration within power electronics systems and their end-use application. The IPEM approach increases the integration in the components that make up a power electronics system through novel a packaging technique known as Embedded Power technology. While the thermal behavior of commonly used packages such as pin grid arrays (PGA), ball grid array (BGA), or quad flat pack (QFP) are well-studied, the influence of the Embedded Power packaging architecture on the overall thermal performance of the IPEMs is not well known. This motivates the presentation of this dissertation in developing an in-depth understanding on the thermal behavior of the Embedded Power modules. In addition, this dissertation outlines some general guidelines for the thermal modeling and thermal testing for the Embedded Power modules. Finally, this dissertation summarizes a few thermal design guidelines for the Embedded Power modules. Hence, this dissertation aims to present significant and generalized scientific findings for the Embedded Power packaging from the thermal perspective. Both numerical and experimental approaches were used in the studies. Three-dimensional mathematical modeling and computational fluid dynamics (CFD) thermal analyses were performed using commercial numerical software, I-DEAS. Experiments were conducted to validate the numerical models, characterize the thermal performance of the Embedded Power modules, and investigate various cooling strategies for the Embedded Power modules. Validated thermal models were used for various thermal analyses including identifying potential thermal problems, recognizing critical thermal design parameters, and exploring different integrated cooling strategies. This research quantifies various thermal design parameters such as the geometrical effect and the material properties on the thermal performance of the Embedded Power modules. These parameters include the chip-to-chip distance, the copper trace area, the polyimide thickness, and the ceramic materials. Since the Embedded Power technology utilizes metallization bonding as interconnection, specific design parameters such as the interconnect via holes pattern and size, the metallization thickness, as well as the metallization materials were also explored to achieve best results based on thermal and stress analyses. With identified potential thermal problems and critical thermal design parameters, different integrated cooling strategies were studied. The concept of integrated cooling is to incorporate the cooling mechanisms into the structure of Embedded Power modules. The results showed that simple structural modifications to the current Embedded Power modules can reduce the maximum temperature of the module by as much as 24%. Further improvement can be achieved by employing double-sided cooling to the Embedded Power modules. Based on the findings from the thermal analyses, general design guidelines were developed for future design of such Embedded Power modules. In addition, thermal modeling and testing guidelines for the Embedded Power modules were also outlined in this dissertation. / Ph. D.

The work reported in this dissertation is intended to propose, analyze and demonstrate a technology for a high temperature integrated power electronics module, for high temperature (e.g those over 200oC) applications involving high density and low stress. To achieve this goal, this study has examined some existing packaging approaches, such as wire-bond interconnects and solder die-attach, flip-chip and pressure contacts. Based on the survey, a high temperature, multilayer 3-D packaging technology in the form of an Embedded Chip Module (ECM) is proposed to realize a lower stress distribution in a mechanically balanced structure with double-sided metallization layers and material CTE match in the structure. Thermal and thermo-mechanical analysis on an ECM is then used to demonstrate the benefits on the cooling system, and to study the material and structure for reducing the thermally induced mechanical stress. In the thermal analysis, the high temperature ECM shows the ability to handle a power density up to 284 W/in3 with a heat spreader only 2.1x2.1x0.2cm under forced convection. The study proves that the cooling system can be reduced by 76% by using a high temperature module in a room temperature environment. Furthermore, six proposed structures are compared using thermo-mechanical analysis, in order to obtain an optimal structure with a uniform low stress distribution. Since pure Mo cannot be electroplated, the low CTE metal Cr is proposed as the stress buffering material to be used in the flat metallization layers for a fully symmetrical ECM structure. Therefore, a chip area stress as low as 126MPa is attained. In the fabrication process, the high temperature material glass and a ceramic adhesive are applied as the insulating and sealing layers. Particularly, the Cr stress buffering layer is successfully electroplated in the high temperature ECM by means of the hard chrome plating process. The flat metallization layer is accomplished by using a combined structure with Cr and Cu metallization layers. The experimental evaluations, including the electrical and thermal characteristics of the ECM, have been part of in the study. The forward and reverse characteristics of the ECM are presented up to 250oC, indicating proper device functionality. The study on the reverse characteristics of the ECM indicates that the large leakage current at high temperature is not due to the package surrounding the chip, but chiefly caused by the Schottky junction and the chip passivation layer. Finally, steady-state and transient measurements are conducted in terms of the thermal measurements. The steady-state thermal measurement is used to demonstrate the cooling system reduction. To obtain the thermal parameters of the different layers in the high temperature ECM, the transient thermal measurement is applied to a single chip ECM based on the temperature cooling-down curve measurement. / Ph. D.

This dissertation presents a systematic design and demonstration of a novel solid-state DC circuit breaker. The mechanical circuit breaker is widely used in power systems to protect industrial equipment during fault or abnormal conditions. Compared with the slow and high-maintenance mechanical circuit breaker, the solid-state circuit breaker is capable of high-speed interruption of high currents without generating an arc, hence it is maintenance-free. Both the switch and the tripping unit are solid-state, which meet the requirements of precise protection and high reliability. The major challenge in developing and adopting a solid-state circuit breaker has been the lack of power semiconductor switches that have adequate current-carrying capability and interruption capability. The high-speed, high-current solid-state DC circuit breaker proposed and demonstrated here uses a newly-emerging power semiconductor switch, the emitter turn-off (ETO) thyristor as the main interruption switch. In order to meet the requirement of being a high-current circuit breaker, ETO parallel operation is needed. Therefore the major effort of this dissertation is dedicated to the development of a high-current (5000A) DC switch module that utilizes multiple ETOs in parallel. This work can also be used to develop an AC switch module by changing the asymmetrical ETOs used to symmetrical ETOs. An accurate device model of the ETO is needed for the development of the high-current DC switch module. In this dissertation a novel physics-base lumped charge model is developed for the ETO thyristor for the first time. This model is verified experimentally and used for the research and development of the emitter turn-off (ETO) thyristor as well as the DC switch module discussed in this dissertation. With the aid of the developed device model, the device current sharing between paralleled multiple ETO thyristors is investigated. Current sharing is difficult to achieve for a thyristor-type device due to the large device parameter variations and strong positive feedback mechanism in a latched thyristor. The author proposes the "DirectETO" concept that directly benefits from the high-speed capability of the ETO and strong thermal couplings among ETOs. A high-current DC switch module based on the DirectETO can be realized by directly connecting ETOs in parallel without the bulky current sharing inductors used in other current-sharing solutions. In order to achieve voltage stress suppression under high current conditions, the parasitic parameters, especially parasitic inductance in a high-current ETO switch module are studied. The Partial Element Equivalent Circuit (PEEC) method is used to extract the parasitics. Combined with the developed device model, the electrical interactions among multiple ETOs are investigated which results in structural modification for the solid-state DC switch module. The electro-thermal model of the DC switch module and the heatsink subsystem is used to identify the "thermal runaway" phenomenon in the module that is caused by the negative temperature coefficient of the ETO's conduction drop. The comparative study of the electro-thermal coupling identifies a strongly-coupled thermal network that increases the stability of the thermal subsystem. The electro-thermal model is also used to calculate the DC and transient thermal limit of the DC switch module. The high-current (5000A) DC switch module coupled with a solid state tripping unit is successfully applied as a high-speed, high-current solid-state DC circuit breaker. The experimental demonstration of a 5000A current interruption shows an interruption time of about 5 microseconds. This high-speed, high-current DC switch module can therefore be used in DC circuit breaker applications as well as other types of application, such as AC circuit breakers, transfer switches and fault current limiters. Since the novel solid-state DC circuit breaker is able to extinguish the fault current even before it reaches an uncontrollable level, this feature provides a fast-acting, current-limiting protection scheme for power systems that is not possible with traditional circuit breakers. The potential impact on the power system is also discussed in this dissertation. / Ph. D.

Miniaturizing circuit size and increasing power density are the latest trends in modern power electronics development. In order to meet the requirements of higher frequency and higher power density in power electronics applications, planar interconnections are utilized to achieve a higher integration level. Power switching devices, passive power components, and EMI (Electromagnetic Interference) filters can all be integrated into planar power modules by using planar metallization, which is a technology involving electrical, mechanical, material, and thermal issues. By processing high dielectric materials, magnetic materials, or silicon chips using compatible manufacturing procedures, and by carefully designing structures and interconnections, we can realize the conventional discrete inductors, capacitors, and switch circuits with planar modules. Compared with conventional discrete components, the integrated planar modules have several advantages including lower profiles, better form factors, and less labor-intensive processing steps. In addition, planar interconnections reduce the wire bond inductive and resistive parasitic parameters, especially for high frequency applications. However, planar integration technology is a packaging approach with a large contact area between different materials. This may result in unknown failure mechanisms in power applications. Extensive research has already been done to study the performance, processing, and reliability of the planar interconnects in thin film structures. The thickness of the thin films used in integrated circuits (IC) or microelectronics applications ranges from the magnitude of nanometers to that of micrometers. In this work, we are interested in adopting planar interconnections to Integrated Power Electronics Modules (IPEM). In Integrated Power Electronics Modules (IPEMs), copper traces, especially bus traces, need to conduct current ranging from a few amps to tens of amps. One of the major differences between IC and IPEM is that the metal layer in IPEMs (normally >75µm) is much thicker than that of the thin films in IC (normally <1µm). The other major difference, which is also a feature of IPEM, is that the planar metallization is deposited on different brittle substrates. In active IPEM, switching devices are in a bare die form with no encapsulation. The copper deposition is on top of the silicon chips and the insulation polyimide layer. One of the key elements for passive IPEM and the EMI IPEM is the integrated inductor-capacitor (LC) module, which realizes equivalent inductors and capacitors in one single module. The deposition processes for silicon substrates and ceramic substrates are compatible and both the silicon and ceramic materials are brittle. Under high current and high temperature conditions, these copper depositions on brittle materials will cause detrimental failure spots. Over the last few years, the design, manufacture, optimization, and testing of the IPEMs has been developed and well documented. Up to this time , the research on failure mechanisms of conventional integrated power modules has led to the understanding of failures centered on wire bond or solder layer. However, investigation on the reliability and failure modes of IPEM is lacking, particularly that which uses metallization on brittle substrates for high current operations. In this study, we conduct experiments to measure and calculate the residual stresses induced during the process. We also, theoretically model and simulate the thermo-mechanical stresses caused by the mismatch of thermal expansion coefficients between different materials in the integrated power modules. In order to verify the simulation results, the integrated power modules are manufactured and subjected to the lifetime tests, in which both power cycling and temperature cycling tests are carried out. The failure mode analysis indicates that there are different failure modes for copper films under tensile or compressive stresses. The failure detection process verifies that delamination and silicon cracks happen to copper films due to compressive and tensile stresses respectively. This study confirms that the high stresses between the metallization and the silicon are the failure drivers in integrated power electronics modules.. We also discuss the driving forces behind several different failure modes. Further understanding of thesefailure mechanisms enables the failure modes to be engineered for safer electrical operation of IPEM modules and helps to enhance the reliability of system-level operation. It is also the basis to improve the design and to optimize the process parameters so that IPEM modules can have a high resistance to recognized failures. / Ph. D.