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The attempts at classification of functional faults in VLSI chips have not been very successful in the past. The problem is blown out of proportions because methods used for testing have not evolved at the same pace as the technology. The fault-models proposed for LSI systems are no longer capable of testing VLSI devices efficiently. Thus the stuck-at and short/open fault models are outdated. Despite this fact, these old models are used in the industry with some modifications. Also, these gate-level fault models are very time-consuming and costly to run on the mainframe computers. In this thesis, a new method is developed for fault modeling at the functional level. This new method called 'Model Perturbation' is shown to be very simple and viable for automation. Some general sets of rules are established for fault selection and insertion. Based on the functional fault model introduced, a method of test vector development is formulated. Finally, the results obtained from functional fault simulation are related to gate level coverage. The validity and simplicity of using these models for combinational and sequential VLSI circuits is discussed. As an example, the modeling of IBM's AMAC chip, the work on which was done under contract YD 190121, is described. / M.S.

This thesis reports the performance of a simple classifier as a function of its training data set. The classifier is used to remove analog tests and is named the Test Removal Classifier (TRC). The thesis proposes seven different training data set designs that vary by the number of wafers in the data set, the source of the wafers and the replacement scheme of the wafers. The training data set size ranges from a single wafer to a maximum of five wafers. Three of the training data sets include wafers from the Lot Under Test (LUT). The training wafers in the data set are either fixed across all lots, partially replaced by wafers from the new LUT or fully replaced by wafers from the new LUT. The TRC's training is based on rank correlation and selects a subset of tests that may be bypassed. After training, the TRC identifies the dies that bypass the selected tests. The TRC's performance is measured by the reduction in over-testing and the number of test escapes after testing is completed. The comparison of the different training data sets on the TRC's performance is evaluated using production data for a mixed-signal integrated circuit. The results show that the TRC's performance is controlled by a single parameter- the rank correlation threshold.

Rapid advancement and innovation in semiconductor research have continuously helped in designing efficient and complex integrated circuits in miniature size. As the device technology, is aggressively scaling to improve the device performance, the issues related to device interconnects, power, and reliability have become a major concern for the designers. These challenges make the design and validation of ASIC extremely complicated. The primary idea of this work is to develop automation tools, to be used in the physical design flows to improve the efficiency of the design flow. The first tool named as variation analysis tool automates the on-chip variation modeling used in the post-layout timing closure phase in the physical design flows. The proposed variation analysis tool models three types of variations such as on-chip variation (OCV), advanced on-chip variation (AOCV) and parametric on-chip variation (POCV). The results of the proposed tool have compared with the Synopsys PrimeTime™ results, and the results show average around 98% accuracy compared to the PrimeTime™. The second tool is for automating repeater analysis in the physical design flows. The repeater automation tool can be used to automate the repeater or buffer insertion process, while technology process is changed from one to another. The tool can calculate the best possible repeater distance for any given metal layer and also, the number of repeaters, combinational or sequential for the user given distance and frequency. The accuracy of this script is compared with the repeater insertion based on the synthesis tools and also, the SPICE simulation.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

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