<p>Den här rapporten innehåller information om hur man skapar en länk mellan en dator och ett minne via en dators serieport. Ett RS232-protokoll används för att upprätthålla den här länken. För att ta hand om minnet samt upprätthålla kommunikationen med datorn har en FPGA programmerats. Intel hex8 formatet används för datan. Ett program för Windows 98 skapades också. Programmet öppnar en fil och läser tecken. Tecknen översätts till heltal som sänds till serieporten. Programmet kan också spara data till en fil. Data hämtas från minnet via serieporten.</p> / <p>This report contains information how to establish a link between a computer and a memory through the serialport of a computer. The RS232 protocol is used to establish this link. To handle the memory and the communication with the computer a FPGA has been programmed. The data is in Intel hex8 format. A program for Windows 98 were also created. The program opens a file and reads characters from it. The charcters are translated into integers which are sent to the serialport. The program can also store data, recieved from the serialport, to a file.</p>

Reproduction de : Mémoire d'ingénieur : informatique : Grenoble, CNAM : 1984. / Titre provenant de l'écran-titre. Bibliogr. p. 142.

Reproduction de : Mémoire d'ingénieur : informatique : Grenoble, CNAM : 1979. / Titre provenant de l'écran-titre. Bibliogr. p. 67.

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnologico / Made available in DSpace on 2016-01-08T19:34:45Z (GMT). No. of bitstreams: 1 99802.pdf: 2570350 bytes, checksum: d5cd4ff545ad452df301395ebf82b8ea (MD5) Previous issue date: 1995 / Foi desenvolvido um conjunto de ferramentas que objetivam auxiliar o desenvolvimento, teste e depuração de softwares para microcomputadores dedicados que utilizam os recursos da arquitetura dos processadores Intel 80386/80486 disponíveis no modo protegido. As ferramentas implementadas permitem a utilização de um PC 386/486 compatível como ambiente de desenvolvimento, além dos compiladores mais populares para as linguagens de programação Assembly e C.

Orientador: Jose Antonio Siqueira Dias / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica / Made available in DSpace on 2018-07-21T10:43:13Z (GMT). No. of bitstreams: 1 Lopes_SilviaElisabethSauaia_M.pdf: 6529088 bytes, checksum: 94361c93b2fa30ab34622f13f5d2b5f3 (MD5) Previous issue date: 1996 / Resumo: Tanques para banho à temperatura constante necessitam de um sistema de controle para monitoração e controle de sua temperatura de operação e demais funções. O controle da temperatura deve ser rígido e preciso; condições de alarme e desligamento automático devem ser previstos. O presente trabalho pretende estudar, implementar e testar um protótipo de um sistema de controle microprocessado para tais tanques. Este trabalho apresenta um controlador digital do tipo PID, baseado na arquitetura do microcontrolador 8051 da Intel, com aIto desempenho, robusto, eficiente e simples, características estas comprovadas através de testes práticos realizados no final do projeto / Abstract: Tanks for constant temperature bath need a temperature and related functions moni toring and control system. Temperature control must be constant and precise; alarm and automatic switching off conditions must be provided. This work is to study, implement and test a microprocessor controller's prototype for such tanks. This work presents a digital controller with a PID control scheme, based in the architecture of the Intel' s 8051 microcontroller, with high performance, strong, efficient and simple, characteristics verified through practical tests made at the end of the project / Mestrado / Mestre em Engenharia Elétrica

Orientador : Celso Cardoso Guimarães / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Matematica, Estatistica e Ciencia da Computação / Made available in DSpace on 2018-07-15T01:40:27Z (GMT). No. of bitstreams: 1 Oyama_Akira_M.pdf: 3071318 bytes, checksum: f94e7eba7c2c5328e8d13af0780fce5f (MD5) Previous issue date: 1984 / Resumo: O trabalho aqui apresentado e' um gerador de código para um Compilador Pascal. O gerador de codigo foi escrito como o segundo passo de um compilador Pascal existente, o compilador NBS para o PDP 11. A maquina objeto e' o microprocessador 8088 da INTEL. o nosso objetivo foi obter um gerador de codigo eficiente em termos de memoria. Os resultados descritos no capitulo 6 mostram que o nosso objetivo foi razoavelmente atingido / Abstract: We present in.this thesis a code generator for a Pascal Compiler. The code genarator was written as the second pass of an existent Pascal Compilar, Pascal NBS for PDP 11. The target machine is the INTEL 8088 microprocessor. Our objective is to obtain an efficient code generator in terms of memory. The results shown in the chapter 6 demonstrate that our objective was reasonably achieved / Mestrado / Mestre em Ciência da Computação

Hardware-Assisted Trusted Execution Environment technologies have become a crucial component in providing security for cloud-based computing. One of such hardware-assisted countermeasures is Intel Software Guard Extension (SGX). Using additional dedicated hardware and a new set of CPU instructions, SGX is able to provide isolated execution of code within trusted hardware containers called enclaves. By utilizing private encrypted memory and various integrity authentication mechanisms, it can provide confidentiality and integrity guarantees to protected data. In spite of dedicated hardware, these extra layers of security add a significant performance overhead. Decryption of data using secret OTPs, which are generated by modified Counter Mode Encryption AES blocks, results in a significant latency overhead that contributes to the overall SGX performance loss. This thesis introduces a metadata prediction extension to SGX based on local metadata releveling and prediction mechanisms. Correct prediction of metadata allows to speculatively precompute OTPs, which can be immediately used in decryption of incoming ciphertext data. This hides a significant part of decryption latency and results in faster SGX performance without any changes to the original SGX security guarantees. / Master of Science / With the exponential growth of cloud computing, where critical data processing is happening on third-party computer systems, it is important to ensure data confidentiality and integrity against third-party access. Sometimes that may include not only external attackers, but also insiders, like cloud computing providers themselves. While software isolation using Virtual Machines is the most common method of achieving runtime security in cloud computing, numerous shortcomings of software-only countermeasures force companies to demand extra layers of security. Recently adopted general purpose hardware-assisted technology like Intel Software Guard Extension (SGX) add that extra layer of security at the significant performance overhead. One of the major contributors to the SGX performance overhead is data decryption latency. This work proposes a novel algorithm to speculatively predict metadata that is used during decryption. This allows the processor to hide a significant portion of decryption latency, thus improving the overall performance of Intel SGX without compromising security.

This thesis discusses small size intercom networks. It is intended for, but not limited to, the use of optical fibre as the interconnecting medium. / Thesis / Master of Engineering (ME)

Approved for public release, distribution is unlimited / In order to address the requirements of the rapidly growing Internet, network processors have emerged as the solution to the customization and performance needs of networking systems. An important component in a network is the router, which receives incoming packets and directs them to specific routes elsewhere in the system. Network processors and the associated software control the routers and switches and allow software designers to deploy new systems such as multicasting forwarder and firewalls quickly.This thesis introduces network processors and their features, focusing on the Intel IXP1200 network processor. A multicast design for the IXP1200 using microACE is proposed. This thesis presents an approach to building a multicasting forwarder using the IXP1200 network processor layer-3 forwarder microACE that carries out unicast routing. The design is based on the Intel Internet exchange architecture and its active computing element (ACE). The layer-3 unicast forwarder microACE is used as a basic starting point for the design. Some software modules, called micoblocks, are modified to create a multicast forwarder that is flexible and efficient. / Lieutenant Junior Grade, Turkish Navy

Aplicações têm tradicionalmente utilizado o paradigma de programação sequencial. Com a recente expansão da computação paralela, em particular os processadores multinúcleo e ambientes distribuídos, esse paradigma tornou-se um obstáculo para a utilização dos recursos disponíveis nesses sistemas, uma vez que a maior parte das aplicações tornam-se restrita à execução sobre um único núcleo de processamento. Nesse sentido, este trabalho de mestrado introduz uma abordagem para paralelizar programas sequenciais de forma automática e transparente, diretamente sobre o código-binário, de forma a melhor utilizar os recursos disponíveis em computadores multinúcleo. A abordagem consiste na desmontagem (disassembly) de aplicações Intel x86 e sua posterior tradução para uma linguagem intermediária. Em seguida, são produzidos grafos de fluxo e dependências, os quais são utilizados como base para o particionamento das aplicações em unidades paralelas. Por fim, a aplicação é remontada (assembly) e traduzida novamente para a arquitetura original. Essa abordagem permite a paralelização de aplicações sem a necessidade de esforço suplementar por parte de desenvolvedores e usuários. / Traditionally, computer programs have been developed using the sequential programming paradigm. With the advent of parallel computing systems, such as multi-core processors and distributed environments, the sequential paradigm became a barrier to the utilization of the available resources, since the program is restricted to a single processing unit. To address this issue, we introduce a transparent automatic parallelization methodology using a binary rewriter. The steps involved in our approach are: the disassembly of an Intel x86 application, transforming it into an intermediary language; analysis of this intermediary code to obtain flow and dependency graphs; partitioning of the application into parallel units, using the obtained graphs and posterior reassembly of the application, writing it back to the original Intel x86 architecture. By transforming the compiled application software, we aim at obtaining a program which can explore the parallel resources, with no extra effort required either from users or developers.