<p>In modern approach to software development, a great importance is given to monitoring &nbsp;of software quality in early development phases. Therefore, static analysis becomes more important. Furthermore, software projects are becoming more complex and heterogeneous. These characteristics are reflected in a diversity of functionalities and &nbsp;variety of computer languages and the technologies used for their development. Because of that consistency in static analysis becomes more important than it was earlier.</p><p>In this dissertation SSQSA: Set of Software Quality Static Analyzers is described. The aim &nbsp;of the SSQSA framework&nbsp; is consistent static analysis. This goal is reached by introducing new intermediate source code representation called eCST: enriched Concrete Syntax Tree. The dissertation mostly focuses on eCST, intermediate representations derived from it, and their generation with description of the&nbsp;<br />tools involved in it.</p><p>The main characteristic of eCST is language independence which gives to SSQSA framework two-level extensibility: supporting a new language and supporting a new &nbsp;analysis. This leads to eciency of adding both level supports and&nbsp;consistency of added functionalities.</p><p>To prove the concept, support for more than 10 characteristic languages was introduced. Furthermore, characteristic static analysis techniques (software metrics calculation,&nbsp;<br />code-clone detection, etc.) were implemented and integrated in the framework.&nbsp;</p><p>Established SSQSA framework provides the infrastructure for the further development of the complete platform for software quality control.</p> / <p>U modernim pristupima razvoju softvera veliki značaj pridaje se kontroli kvaliteta softvera u ranim fazama razvoja.&nbsp;Zbog toga, statička analiza postaje sve značajnija. Takođe,&nbsp;softverski proizvodi postaju sve kompleksniji i heterogeni.&nbsp;Ove karakteristike se ogledaju u raznovrsnosti jezika i&nbsp;tehnologija koje se koriste u procesu razvoja softvera. Zbog&nbsp;toga, konzistentnost u statičkoj analizi dobija veći značaj&nbsp;nego &scaron;to je to bio slučaj ranije.</p><p>U ovoj disertaciji opisan je SSQSA skup statičkih analizatora&nbsp;za kontrolu kvaliteta (eng. Set of Software Quality Static&nbsp;Analyzers). Namena SSQSA okvira je konzistentna statička&nbsp;analiza. Cilj se postiže uvođenjem nove međureprezentacije&nbsp;<br />izvornog koda nazvane eCST (obogaćeno konkretno sintaksno stablo, eng. enriched &nbsp;Concrete Syntax Tree).&nbsp;Fokus disertacije je primarno na eCST reprezenataciji koda,&nbsp;<br />reprezentacijama izvedenjim iz eCST i procesu njihovog&nbsp;generisanja, sa opisom oruđa angažovanim u ovim procesima.</p><p>Osnovna i najbitnija karakteristika eCST reprezenatacije&nbsp;je nezavisnost od jezika u kom je izvorni kod pisan, &scaron;to&nbsp;SSQSA okviru daje pro&scaron;irivost na dva nivoa: kroz podr&scaron;ku&nbsp;za nove jezike i kroz podr&scaron;ku za nove analize. Ovo dovodi do&nbsp;efikasnog uvođenja funkcionalnosti na oba navedena nivoa,&nbsp;kao i do konzistentnosti uvedenih funkcionalnosti.&nbsp;</p><p>Kao dokaz ispravnosti koncepta, podr&scaron;ka za vi&scaron;e od 10&nbsp;ulaznih jezika je uvedena. Takođe, implementirane su karakteristične tehnike statičke analize (izračunavanje softverskih&nbsp;metrika, otkrivanje duplikata u kodu, itd.) i integrisane u&nbsp;SSQSA okvir.&nbsp;</p><p>Na opisani način, postavljanjem SSQSA okvira, obezbeđena&nbsp;je infrastruktura za dalji razvoj kompletne platforme za kontrolu kvaliteta softvera.&nbsp;</p>

As transistors size and power limitations stroke computer industry, hardware parallelism arose as the solution, bringing old forgotten problems back into equation to solve the existing limitations of current parallel technologies. Compilers regain focus by being the most relevant puzzle piece in the quest for the expected computer performance improvements predicted by Moores law no longer possible without parallelism. Parallel research is mainly focused in either the language or architectural aspects, not really giving the needed attention to compiler problems, being the reason for the weak compiler support by many parallel languages or architectures, not allowing to exploit performance to the best. This thesis addresses these problems by presenting: Erbium, a low level streaming data-flow language supporting multiple producer and consumer task communication; a very efficient runtime implementation for x86 architectures also addressing other types of architectures; a compiler integration of the language as an intermediate representation in GCC; a study of the language primitives dependencies, allowing compilers to further optimise the Erbium code not only through specific parallel optimisations but also through traditional compiler optimisations, such as partial redundancy elimination and dead code elimination.

One of the most difficult tasks a compiler writer faces is the construction of the instruction selector. The instruction selector is that part of the compiler that translates compiler intermediate representation (IR) into instructions for a target machine. Unfortunately, implementing an instruction selector “by hand” is a difficult, time consuming, and error prone task. The details of both the IR and target instruction set must be carefully considered in order to generate correct and efficient code. This, in turn, requires an expert in both the compiler internals as well as the target machine. Even an expert, however, can implement an instruction selector that is difficult to verify and debug. In this dissertation we describe the instruction selector problem, cover previous attempts at solving it, and identify what we believe to be the most prominent factor inhibiting their widespread adoption. This dissertation proposes a generalized approach toward generating instruction selectors automatically. In particular, we propose CISL, a common machine description language for specifying the semantics of compiler IR and target instructions, and GIST, a machine independent heuristic search procedure that can find equivalent instruction sequences between compiler IR and target instructions. CISL is an object-oriented-based language leveraging modern programming language constructs (e.g., classes, inheritance, mixins) and is capable of describing instructions for a variety of IR and target ISAs (Instruction Set Architecture). GIST leverages CISLs well-defined semantics and a canonicalization process to discover automatically instruction selector patterns: target instruction sequences that implement IR semantics. These instruction selector patterns are then generated in a compiler implementation independent format (XML). Small adapter programs use the generated instruction selector patterns to generate compiler specific implementation code. Our experiments show that instruction selector patterns can be discovered automatically and independent of a particular compiler framework or target machine. In addition, experience proved that adapter programs are easy to implement and instruction selector code is easy to generate from generated patterns. Furthermore, the generated instruction selectors are comparable in performance to the original compilers.

No description available.

Frappée par les rendements décroissants de la performance séquentielle et les limitations thermiques, l’industrie des microprocesseurs s’est tournée résolument vers les multiprocesseurs sur puce. Ce mouvement a ramené des problèmes anciens et difficiles sous les feux de l’actualité du développement logiciel. Les compilateurs sont l’une des pièces maitresses du puzzle permettant de poursuivre la traduction de la loi de Moore en gains de performances effectifs, gains inaccessibles sans exploiter le parallélisme de threads. Pourtant, la recherche sur les systèmes parallèles s’est concentrée sur les aspects langage et architecture, et le potentiel reste énorme en termes de compilation de programmes parallèles, d’optimisation et d’adaptation de programmes parallèles pour exploiter efficacement le matériel. Cette thèse relève ces défis en présentant Erbium, un langage de bas niveau fondé sur le traitement de flots de données, et mettant en œuvre des communications multi-producteur multi-consommateur ; un exécutif parallèle très efficace pour les architectures x86 et des variantes pour d’autres types d’architectures ; un schéma d’intégration du langage dans un compilateur illustré en tant que représentation intermédiaire dans GCC ; une étude des primitives du langage et de leurs dépendances permettant aux compilateurs d’optimiser des programmes Erbium à l’aide de transformations spécifiques aux programmes parallèles, et également à travers des formes généralisées d’optimisations classiques, telles que l’élimination de redondances partielles et l’élimination de code mort. / As transistors size and power limitations stroke computer industry, hardware parallelism arose as the solution, bringing old forgotten problems back into equation to solve the existing limitations of current parallel technologies. Compilers regain focus by being the most relevant puzzle piece in the quest for the expected computer performance improvements predicted by Moores law no longer possible without parallelism. Parallel research is mainly focused in either the language or architectural aspects, not really giving the needed attention to compiler problems, being the reason for the weak compiler support by many parallel languages or architectures, not allowing to exploit performance to the best. This thesis addresses these problems by presenting: Erbium, a low level streaming data-flow language supporting multiple producer and consumer task communication; a very efficient runtime implementation for x86 architectures also addressing other types of architectures; a compiler integration of the language as an intermediate representation in GCC; a study of the language primitives dependencies, allowing compilers to further optimise the Erbium code not only through specific parallel optimisations but also through traditional compiler optimisations, such as partial redundancy elimination and dead code elimination.

In order to take the performance advantages of the current multicore and heterogeneous architectures the compilers are required to perform more and more complex program transformations. The search space of the possible program optimizations is huge and unstructured. Selecting the best transformation and predicting the potential performance benefits of that transformation is the major problem in today's optimizing compilers. The promising approach to handling the program optimizations is to focus on the automatic loop optimizations expressed in the polyhedral model. The current approaches for optimizing programs in the polyhedral model broadly fall into two classes. The first class of the methods is based on the linear optimization of the analytical cost function. The second class is based on the exhaustive iterative search. While the first approach is fast, it can easily miss the optimal solution. The iterative approach is more precise, but its running time might be prohibitively expensive. In this thesis we present a novel search-based approach to program transformations in the polyhedral model. The new method combines the benefits - effectiveness and precision - of the current approaches, while it tries to minimize their drawbacks. Our approach is based on enumerating the evaluations of the precise, nonlinear performance predicting cost-function. The current practice is to use the polyhedral model in the context of source-to-source compilers. We have implemented our techniques in a GCC framework that is based on the low level three address code representation. We show that the chosen level of abstraction for the intermediate representation poses scalability challenges, and we show the ways to overcome those problems. On the other hand, it is shown that the low level IR abstraction opens new degrees of freedom that are beneficial for the search-based transformation strategies and for the polyhedral compilation in general.

Decompilation or reverse compilation is the process of translating low-level machine-readable code into high-level human-readable code. The problem is non-trivial due to the amount of information lost during compilation, but it can be divided into several smaller problems which may be solved independently. This report explores the feasibility of composing a decompilation pipeline from independent components, and the potential of exposing those components to the end-user. The components of the decompilation pipeline are conceptually grouped into three modules. Firstly, the front-end translates a source language (e.g. x86 assembly) into LLVM IR; a platform-independent low-level intermediate representation. Secondly, the middle-end structures the LLVM IR by identifying high-level control flow primitives (e.g. pre-test loops, 2-way conditionals). Lastly, the back-end translates the structured LLVM IR into a high-level target programming language (e.g. Go). The control flow analysis stage of the middle-end uses subgraph isomorphism search algorithms to locate control flow primitives in CFGs, both of which are described using Graphviz DOT files. The decompilation pipeline has been proven capable of recovering nested pre-test and post-test loops (e.g. while, do-while), and 1-way and 2-way conditionals (e.g. if, if-else) from LLVM IR. Furthermore, the data-driven design of the control flow analysis stage facilitates extensions to identify new control flow primitives. There is huge potential for future development. The Go output could be made more idiomatic by extending the post-processing stage, using components such as Grind by Russ Cox which moves variable declarations closer to their usage. The language-agnostic aspects of the design will be validated by implementing components in other languages; e.g. data flow analysis in Haskell. Additional back-ends (e.g. Python output) will be implemented to verify that the general decompilation tasks (e.g. control flow analysis, data flow analysis) are handled by the middle-end. / <p>BSc dissertation written during an ERASMUS exchange from Uppsala University to the University of Portsmouth.</p>

The Discrete Fourier Transform (DFT) and its improved formulations, the Fast Fourier Transforms (FFTs), are vital for scientists and engineers in a range of domains from signal processing to the solution of partial differential equations.  A growing trend in Scientific Computing is heterogeneous computing, where accelerators are used instead or together with CPUs. This has led to problems for developers in unifying portability, performance, and productivity.  This thesis first motivates this work by showing the importance of having efficient DFT calculations, describes the DFT algorithm and a formulation based on matrix-factorizations which has been developed to formulate FFT algorithms and express their parallelism to exploit modern computer architectures, such as accelerators. The first paper is a motivating study of the breakdown of the performance and scalability of the high-performance Molecular Dynamics code GROMACS where DFT calculations are a main performance bottleneck. In particular, the long-range interactions are solved with the Particle-Mesh Ewald algorithm which uses a three-dimensional Fast Fourier Transform.  The two following papers present two approaches to leverage factorization with the help of two different frameworks using Intermediate Representation and compiler technology, for the development of fast and portable code. The second paper presents a front-end and a pipeline for code generation in a domain-specific language based on Multi-Level Intermediate Representation (MLIR) for developing Fast Fourier Transform libraries. The last paper investigates and optimizes an implementation of an important kernel within the matrix-factorization framework: the batched DFT. It is implemented with data-centric programming and a data-centric intermediate representation called Stateful Dataflow multi-graphs (SDFG). The paper evaluates strategies for complex-valued data layout for performance and portability and we show that there is a trade-off between portability and maintainability in using the native complex data type and that an SDFG-level abstraction could be beneficial for developing higher-level applications. / Den diskreta Fouriertransformen och dess snabba implementeringar är viktiga för vetenskap och ingenjörskonst. Den har tillämningar i ämnen som singnal behnadling, lösning av partiella diffrentialekvationer och många andra ämnen inom vetenskapliga beräkningar. En växande trend inom ämnet är heterogena datorer där acceleratorer som är specialicerade till vissa beräkningar kan användas som stöd för traditionella processorer. Detta leder till problem med portabilitet, prestanda och produktivitet.  Avhandligen inleds med att beskriva diskret Fouriertransform och ett ramverk för faktorisering till glesa strukturerade matriser som tillsammans representerar snabb Fouriertransform (FFT, Eng.) och som kan användas för att uttrycka parallelism i algorithmerna. För att motivera arbete med FFT i vetenskapliga beräkningar så utväreras den parallela prestandan av GROMACS: en kod för simulering av Molekyldynmik. GROMACS använder en tredimensionell diskret Fouriertransform för att finna den elektrostatiska potentialen med hjälp av Particle-Mesh Ewald-tekniken.  De följande två artiklarna presenterar två olika ramverk för att utnyttja mellankod (IR Eng.) och kompilatorteknik, för utvecklandet av  snabb och portabel kod. Den andra artikeln beskriver arbetet att utveckla ett domänspecifikt språk baserat på Multi-Level Intermediate Representation för design av snabba Fouriertransformer baserat på matrisfaktorisering. Den sista artikeln undersöker och optimerar en viktig komponent för matrisfaktorisering av diskreta Fouriertransformen: att beräkna flera små diskreta Fouriertransformer parallelt. Detta är gjort med DaCe som är ramverk för data-centrisk programmering som använder en mellankod kallad SDFG. I artikeln utvärderas strategier för data format av komplexa tal för prestanda och portabilitet, och visar att en abstraktion med hjälp av SDFG kan motiveras. / <p>QC 20230522</p>

The current trend in embedded systems design is to move the initial design and exploration phase to a higher level of abstraction, in order to tackle the rapidly increasing complexity of embedded systems. One approach of abstracting software development from the low level platform details is host- compiled simulation. Characteristics of the target platform are represented in a host-compiled simulation model by annotating the high level source code. Compiler optimizations make accurate annotation of the code a challenging task. In this thesis, we describe an approach to enable correct back-annotation of C code at the basic block level, while taking compiler optimizations into account. / text

Une carte multi-échelle est un ensemble de cartes à différentes échelles, dans lequel l’utilisateur peut naviguer via un géoportail. Chacune de ces cartes est préalablement construite par généralisation cartographique, processus qui adapte la représentation cartographique à une échelle donnée. Les changements de représentations qu’implique la généralisation entre deux cartes à différentes échelles sont susceptibles de perturber l’utilisateur, rendant sa navigation plus difficile. Nous proposons dans cette thèse d’ajouter des représentations intermédiaires dans une carte multi-échelle existante, pour créer une évolution plus fluide du contenu cartographique au fil des échelles. Alors que de solides connaissances théoriques existent pour la conception cartographique traditionnelle, on ne sait pas encore comment concevoir une carte multi-échelle efficace. Pour formaliser des connaissances à ce sujet, nous avons étudié un panel de seize cartes multi-échelles existantes. Nous avons analysé les systèmes de zoom utilisés ainsi que l’évolution des représentations cartographiques au fil des échelles, en particulier les changements de niveaux d’abstraction pour les objets bâtis et routiers. Nous avons aussi évalué la variation de complexité visuelle du contenu cartographique au fil des échelles, en utilisant des mesures de clutter visuel. Nous avons ainsi identifié les tendances générales en termes de représentations multi-échelles (comme l’application du standard WMTS), certains facteurs que nous considérons comme ayant une influence négative sur la navigation de l’utilisateur (comme l’utilisation d’une même carte à différentes échelles), ainsi que des pratiques intéressantes visant à la faciliter (comme les représentations mixtes). A partir de ces constats, nous avons formulé des hypothèses sur l’influence des variables de construction des représentations intermédiaires sur la fluidité de navigation. Nous avons construit un matériel de test à partir d’un extrait de la carte multi-échelle Scan Express de l’IGN, entre les cartes existant au 1 : 25k et au 1 : 100k. Nous avons ainsi produit quatre versions différentes de représentations intermédiaires entre ces deux cartes, implémentant nos différentes hypothèses. Cet exercice nous a permis de mieux cerner les verrous techniques que soulève la production de représentations intermédiaires. Nous avons enfin conduit un test utilisateurs contrôlé, en demandant à 15 participants de réaliser une tâche cartographique sur ces différentes cartes multi-échelles, pour évaluer la pertinence de nos hypothèses / A multi-scale map is a set of maps at different scales, displayed on mapping applications, in which users may navigate by zooming in or out. Each of these maps is produced beforehand by cartographic generalization, which aims to adapt the cartographic representation for a target scale. Due to generalization, the representation changes between maps at different scales may disturb the user during its navigation. We assume that adding intermediate representations in an existing multi-scale map may enable a smooth evolution of cartographic content across scales. While theoretical knowledge exists for traditional cartography, we still do not know how to design efficient multi-scale maps. To formalize knowledge on that subject, we studied sixteen existing multi-scale maps. We focused on the used zooming system (zoom levels and display scales) and on the evolution of cartographic representations across scales, in particular for building and road entities. We also analyzed the variation of visual complexity of the map content across scales, using visual clutter measures. We thus identified general trends in terms of multi-scale representation (i.e. use of WMTS standard), some potential disturbing factors (i.e. use of a same map at different scales), but also good practices which may ease the user navigation (i.e. mixed representations). Based on these findings, we made assumptions on the influence of intermediate representations design on user navigation. We built test material from an extract of the Scan Express multi-scale map of the French IGN, between the existing maps at 1:25k and 1:100k scales. We thus produced four different versions of intermediate representations between these two maps, implementing our different hypotheses. This way, we highlighted the technical issues that we faced when producing intermediate representations. Finally, we conducted a controlled user study, asking 15 participants to perform a cartographic task on these different multi-scale maps, to evaluate our hypotheses