In the application of power inverters, power density has become a key design specification where it has stringent requirements on system size and weight. Achieving high power density need to combine lasted wide bandgap (WBG) device technology and high switching frequency to reduce passive filter size thus further shrink overall space. While still maintaining decent power conversion efficiency and low electromagnetic interference (EMI) with higher switching frequency, soft-switching needs to be implemented. A novel auxiliary resonant snubber is introduced. The design and operation are carried out, in which this snubber circuitry enables main Gallium Nitride (GaN) switches operating under zero voltage switching (ZVS) condition, and auxiliary Silicon Carbide (SiC) diodes switching under zero current switching (ZCS) condition. Besides, the auxiliary snubber circuitry gating algorithm is also optimized which allows reduction of the switching and conduction loss in auxiliary GaN switches to obtain higher system efficiency and better thermal performance. Here, this novel auxiliary resonant snubber circuitry is applied to a traditional full bridge inverter with flexible modulation suitability. This proposed inverter can be applied to a wide range of potential applications, such as string solar inverter, renewable energy combined distributed generation, dc-ac part of bi-directional electrical vehicle (EV) on-board charger, and uninterruptible power supply (UPS), etc. / Master of Science

A multilevel Space Vector PWM (SVPWM) technique is developed for a 3-level 3-phase PWM Voltage Source Inverter using a 3-phase coupled inductor to ensure high performance operation. The selection of a suitable PWM switching scheme for the Coupled Inductor Inverter (CII) topology should be based on the dual requirements for a high-quality multilevel PWM output voltage together with the need to minimize high frequency currents and associated losses in the coupled inductor and the inverter switches. Compared to carrier-based multilevel PWM schemes, the space vector techniques provide a wider variety of choices of the available switching states and sequences. The precise identification of pulse placements in the SVPWM method is used to improve the CII performance. The successful operation of the CII topology over the full modulation range relies on selecting switching states where the coupled inductor presents a low winding current ripple and a high effective inductance between the upper and lower switches in each inverter leg. In addition to these requirements, the CII operation is affected by the imbalance inductor common mode dc current. When used efficiently, SVPWM allows for an appropriate balance between the need to properly manage the inductor winding currents and to achieve harmonic performance gains. A number of SVPWM strategies are developed, and suitable switching states are selected for these methods. Employing the interleaved PWM technique by using overlapping switching states, the interleaved Discontinuous SVPWM (DSVPWM) method, compared to other proposed SVPWM methods, doubles the effective switching frequency of the inverter outputs and, as a result, offers superior performance for the CII topology by reducing the inductor losses and switching losses. The inverter operation is examined by means of simulation and experimental testing. The experimental performance comparison is obtained for different PWM switching patterns. The inverter performance is affected by high-frequency inductor current ripple; the excessive inductor losses are reduced by the DSVPWM method. Additional experimental test results are carried out to obtain the inverter performance as a variable frequency drive when operated in steady-state and during transient conditions. The CII topology is shown to have great potential for variable speed drives. / Power Engineering and Power Electronics

No description available.

Fluorescent lamps are in general driven by ac ballasting currents. The cyclic variation in arc discharging power results in light fluctuation at twice the frequency of the ac current. Light fluctuation may be intolerable when a steady light output is required in some particular applications. To eliminate light fluctuation, an electronic ballast with dc current is proposed to operate the fluorescent lamp at a constant power. The main power conversion of the electronic ballast employs the single-stage high-power-factor inverter, which is originated from a combination of the half-bridge resonant inverter and the buck-boost converter. With such a circuit configuration, the output power can be regulated by asymmetrical pulse-width-modulation. The ac output of the inverter is then rectified and filtered to provide the dc ballasting current. Driven by dc current, however, the fluorescent lamp emits electrons unilaterally from one end leading to wearing out of emission material on the cathode filament. To solve this problem, an inverter is integrated for commutation of the lamp electrodes. Furthermore, a preheating control is included to start the fluorescent lamps with zero glow-current. A prototype is designed and built for the OSRAM T5-80W fluorescent lamp. The dc operating characteristics of starting transient, light fluctuation, lighting spectra, color temperature as well as the light fluctuation are investigated from experiments. Experimental results also show that the electronic ballast is capable of high-power-factor, dimming capability and zero glow-current preheating.

No description available.

abstract: A new photovoltaic (PV) array power converter circuit is presented. The salient features of this inverter are: transformerless topology, grounded PV array, and only film capacitors. The motivations are to reduce cost, eliminate leakage ground currents, and improve reliability. The use of Silicon Carbide (SiC) transistors is the key enabling technology for this particular circuit to attain good efficiency. Traditionally, grid connected PV inverters required a transformer for isolation and safety. The disadvantage of high frequency transformer based inverters is complexity and cost. Transformerless inverters have become more popular recently, although they can be challenging to implement because of possible high frequency currents through the PV array's stay capacitance to earth ground. Conventional PV inverters also typically utilize electrolytic capacitors for bulk power buffering. However such capacitors can be prone to decreased reliability. The solution proposed here to solve these problems is a bi directional buck boost converter combined with half bridge inverters. This configuration enables grounding of the array's negative terminal and passive power decoupling with only film capacitors. Several aspects of the proposed converter are discussed. First a literature review is presented on the issues to be addressed. The proposed circuit is then presented and examined in detail. This includes theory of operation, component selection, and control systems. An efficiency analysis is also conducted. Simulation results are then presented that show correct functionality. A hardware prototype is built and experiment results also prove the concept. Finally some further developments are mentioned. As a summary of the research a new topology and control technique were developed. The resultant circuit is a high performance transformerless PV inverter with upwards of 97% efficiency. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2014

Modern power systems require multiple conversions between DC and AC to deliver power from renewable energy sources. Recent growth in DC loads result in increased system costs and reduced efficiency, due to redundant conversions. Advances in DC microgrid systems demonstrate superior performance by reducing conversion stages. The literature reveals practical DC microgrid systems composed of wind and solar power to replace existing fossil fuel technologies for residential consumers. Although higher efficiencies are achieved, some household appliances require AC power; thus, the need for highly efficient DC to AC converters is imperative in establishing DC microgrid systems. Resonant inverter topologies exhibit zero current switching (ZCS); hence, eliminate switching losses leading to higher efficiencies in comparison to hard switched topologies. Resonant inverters suffer severe limitations mainly attributed to a load dependent resonant frequency. Recent advancements in power electronics propose an electronically tunable inductor suited for low frequency applications [24], [25]; as a consequence, frequency stability in resonant inverters is achievable within a limited load range. This thesis characterizes the operational characteristics of a low-frequency series loaded resonant inverter using a manually tunable inductor to achieve frequency stability and determine feasibility of utilization. Simulation and hardware results demonstrate elimination of switching losses via ZCS; however, significant losses are observed in the resonant inductor which compromises overall system efficiency. Additionally, harmonic distortion severely impacts output power quality and limits practical applications.

Tento projekt zkoumá vybrané způsoby implementace víceúrovňových měničů do praxe. V předložené práci je do hloubky prezentována tzv. ANPC (Active Neutral Point Clamped) pětiúrovňová topologie. Autor se v práci zaměřuje zejména na návrh technického řešení experimentálního vzorku a implementaci řídicích algoritmů jako jsou aktivní řízení napětí na pomocném kondenzátoru nebo aktivní balancování vstupního kapacitního děliče. Pro aplikaci zmíněných struktur byl vybrán moderní digitální integrovaný obvod, který slučuje mikroprocesor a FPGA do jednoho systému. Výsledný měnič umožňuje autonomní provoz a umožňuje generovat přesné a stabilní výstupní napětí.

Using an inverter-driven compressor in variable capacity heat pump systems has a main drawback, which is the extra loss in the inverter. The present experimental study aims to recover the inverter losses by using brine-cooled and water-cooled inverters, thereby improving the total efficiency of the heat pump system. In order to achieve this goal, a test rig with the air-cooled, water-cooled and brine-cooled inverters is designed and built, and a comparative analysis of the recovered heat, inverter losses and system performance is conducted when the compressor is driven by the water-cooled, brine-cooled and air-cooled inverters at three different switching frequencies for each inverter. The experimental results show that the inverter losses as a magnitude and as a ratio of the total consumed power are lowest in the brine-cooled inverter and highest in the air-cooled one at all the compressor speeds and all the inverter switching frequencies. Moreover, the recovered energy varies between 45 and 125 (W) in the water-cooled inverter, which corresponds to 63 and 69 (%) of the inverter losses; while it varies between 61 and 139 (W) in the brine-cooled inverter, which corresponds to 79 and 90 (%) of the inverter losses. It is also proved that the improvement of the system coefficient of performance (COPsys) is almost the same when the water-cooled or the brine-cooled inverter is used and varies between 0.54 and 3 (%) in comparison with using the air-cooled one. Indeed, the total isentropic efficiency of the compressor is improved slightly when using the water-cooled inverter and little more when using the brine-cooled one at the same running conditions. In addition, the total isentropic efficiency of the compressor is improved by increasing the inverter switching frequency when any of the inverters is used. The experimental results also show that cooling the inverter by the water, which comes out from the condenser, increases the maximum temperature of the base plate of the inverter about 10 °C which could cause a two-fold deterioration in the inverter median life in comparison with cooling the inverter by air. On the contrary, using the brine for cooling the inverter decreases the maximum temperature of the base plate of the inverter about 30 °C which could cause about a six-fold improvement in the inverter median life. / Capacity-controlled Ground Source Heat Pump single-family dwellings

Cette thèse porte sur la conception et la réalisation de convertisseurs analogique/numérique (ADC) haute résolution dans le domaine de l’imagerie spatiale en technologie 0.18 μm.Un imageur CMOS est un système destiné à acquérir des informations lumineuses et les convertir en données numériques afin que cellesci soient traitées. Ce système est composé d’une matrice de pixels, d’ADC, de registres et de blocs de signaux de commande afin de rendre toutes ces données disponibles. Avec la taille grandissante de la matrice de pixels et la cadence d’image par seconde croissante, l’ADC doit réaliser de plus en plus de conversions en moins de temps et est donc devenu l’un des « bottleneck » les plus importants dans les systèmes d’imagerie. Une solution adaptée a donc été le développement d’ADC colonne situé en bout de colonnes de pixels afin de réaliser des conversions en parallèles et c’est ce sujet qui va m’intéresser.Dans une première partie, n’ayant pas de contraintes sur l’architecture d’ADC à utiliser, une étude de l’état de l’art des ADC pour l’imagerie est réalisée ainsi que les spécifications visées pour notre application. Une architecture sigma-delta incrémental à deux étapes semble la plus prometteuse et va être développée. Ensuite, une étude théorique de l’ADC choisi, et plus particulièrement du modulateur sigma-delta à utiliser est effectuée, afin notamment de déterminer l’ordre de ce modulateur, mais également le nombre de cycles de cette conversions. Une fois les paramètres de modélisation définis, un schéma transistor est réalisé au niveau transistor, avec une particularité au niveau de l’amplificateur utilisé. En effet, afin de gagner en surface qui est l’un des points importants dans les systèmes d’imagerie, un inverseur est utilisé. Une étude de cette inverseur, afin de choisir le plus adapté à notre besoin est effectuée avec des simulations montecarlo et aux « corners ». Pour finir, un routage global de l’ADC est réalisé afin de pouvoir comparer ces performances à l’état de l’art. / This thesis deals with the conception and design of high resolution analog-to-digital converters (ADC) for CMOS image sensor (CIS) applications with the 0.18 μm technology. A CIS is a system able to convert light to digital data to be processed. This system includes a pixel array, ADCs, registers and a set of clocks to acquire and transport the data. At the beginning, a single ADC was used for the whole matrix of pixels, converting the pixel value in a sequential way. With the growing size of the pixel array and the increasing frame rate, the ADC became one of the bottleneck of these system. A solution was found to use column ADC, located at the bottom of each column in order to parallelize the conversions. These column ADC are going to be my point of interest in this thesis.First of all, a state of the art of the ADC for CIS is realized in order to determine the best architecture to use. A two-step incremental sigma-delta is chosen and investigated. A theoretical analysis is done, especially on the modulator in order to determine the order of this modulator and the oversampling ratio of the conversion. Then a schematic is realized, with a special feature on the amplifier. Indeed, an inverter is used as amplifier in order to reduce the size of the ADC. A montecarlo and corner studies are then realized on the ADC, a layout is proposed and the ADC is compared to the state of the art of the ADC for CIS.