Testing a PCB assembly can be very time consuming due to its complexity andcompactness. Tests are desired to be consistent and test coverage should be as highas possible, which is perfect for automated testing software.This thesis intends to develop computer controlled tests of faulty PCB assembliesusing boundary scan, which is meant to quickly locate the error so that an analysisengineer can evaluate it and prevent it from happening in future versions of theproduct. Boundary scan is even able to test the inner circuitry.Testing with boundary scan has been around for quite some time, but in recentyears it has shown to be truly valuable and time saving, due to the increasingcomplexity of PCB assemblies. The conclusions reached in this study are promisingfor future tests and development of PCBs using boundary scan, which has shownto be quite the powerful tool.

<p>The boundary scan standard which has been in existence since the early nineties is widely used to test printed circuit boards (PCB). It is primarily aimed at providing increased physical test access to surface mounted devices on printed circuit boards (PCB). Using boundary scan avoids using functional testing and In-circuit-techniques like '<em>bed of nails</em>' for structurally testing PCBs as increasing densities and complexities made opting for them a herculean task. Though the standard has had a revolutionizing effect on board testing conducted during the development and production phases, there is a lack of a standardized mechanism to allow IEEE 1149.1 to be used in a system post installation. This has led to problems typically encountered during field test runs, like the issue of high number of No-Fault-Found (NFF), being left unaddressed. The solution lies in conducting a structural test after a given module has already been installed in the system. This can be done by embedding the programmability features of the boundary scan test mechanism into the Unit under test (UUT) thereby enabling the UUT to conduct boundary scan based self tests without the need of external stimuli. In this thesis, a test and debug framework, which aims to use boundary-scan in post system-installation, is the subject of a study and subsequent enhancement. The framework allows embedding much of the test vector deployment and debug mechanism onto the Unit under test (UUT) to enable its remote testing and debug. The framework mainly consists of a prototype board which, along with the UUT, comprise the 'embedded system'. The following document is a description of the phased development of above said framework and its intended usage in the field.</p>

The boundary scan standard which has been in existence since the early nineties is widely used to test printed circuit boards (PCB). It is primarily aimed at providing increased physical test access to surface mounted devices on printed circuit boards (PCB). Using boundary scan avoids using functional testing and In-circuit-techniques like 'bed of nails' for structurally testing PCBs as increasing densities and complexities made opting for them a herculean task. Though the standard has had a revolutionizing effect on board testing conducted during the development and production phases, there is a lack of a standardized mechanism to allow IEEE 1149.1 to be used in a system post installation. This has led to problems typically encountered during field test runs, like the issue of high number of No-Fault-Found (NFF), being left unaddressed. The solution lies in conducting a structural test after a given module has already been installed in the system. This can be done by embedding the programmability features of the boundary scan test mechanism into the Unit under test (UUT) thereby enabling the UUT to conduct boundary scan based self tests without the need of external stimuli. In this thesis, a test and debug framework, which aims to use boundary-scan in post system-installation, is the subject of a study and subsequent enhancement. The framework allows embedding much of the test vector deployment and debug mechanism onto the Unit under test (UUT) to enable its remote testing and debug. The framework mainly consists of a prototype board which, along with the UUT, comprise the 'embedded system'. The following document is a description of the phased development of above said framework and its intended usage in the field.

Debugging and testing today's complex processors and embedded systems provides many challenges. A Debug and Trace Probe with a standard interface to Target Systems (TS) can be used to debug and test both hardware and software components in complex systems. With a debug and trace probe information regarding the operation of the system can be obtained and analyzed to understand how the system is functioning and where problems may lie. This report presents an IEEE 1149.7-compliant cJTAG Controller design and implmentation for use in a Debug and Trace System (DTS). / text

The Versal Adaptive Compute Acceleration Platform (Versal ACAP) is a system-on-chip (SoC) developed by AMD Xilinx. To help protect the programmable logic from soft errors, the configuration needs to be constantly checked and repaired through a process called scrubbing. This thesis provides a methodology for scrubbing the configuration over JTAG. The scrubber uses two platform device image (PDI) files, one to read the configuration and one to send corrected frames. The methodology is characterized to determine the time it takes to completely scrub the configuration. The designed scrubber was able to scrub the VM1802 in 11.5 seconds, or 41.6 Mbits/second, when the JTAG interface was operated at 50MHz.

This master‘s final paper describes JTAG (boundary scan) interface in which discuss IEEE standart 1149.1 circuit model and the main TAP (Test Access Port) controllers instructions. Accomplished programmable integral logical ICs overview: development, leading manufacturer (ALTERA, XILINX, ACTEL) production and programmable equipment evaluation. Represented recomendation, how we can pick suitable programmable logical device. The paper presents detailed describe searching ICs family XC9500 characteristic, features and merits. In general terms presented programmable logic language VHDL value. It also produces some detailed compose describes of the project, using methods of circuit drawing and VHDL language. Master‘s hypothesis that if we will use JTAG interface processed logical programmable instrumentation in our projects we can save up time, area and improve their quality is confirmed. This is prospective technology which also soon will be in use in Lithuania.

Ett projekt har genomförts i python för att läsa och analysera nätlistor från eCAD programmet Altium. Projektet är en prototyp till en mjukvara som färdigutvecklad ska kunna användas till att automatisera kontakttest på mönsterkort mha JTAG Boundary Scan. Projektet undersöker hur stor andel av kontaktbanorna på några godtyckligt valda mönsterkort som är tillgängliga för Boundary Scan test och finner att i snitt 39% av kontaktbanorna är observerbara.

SRAM-based Field Programmable Gate Arrays (FPGAs) must be programmed with configuration data every time they are powered on. In addition to initially programming an FPGA, there are many other applications that require access to FPGA configuration memory such as partial reconfiguration, fault injection, and memory scrubbing. This thesis describes a system that provides high-speed, programmable configuration management for Xilinx FPGAs through external interfaces. This system is an improvement upon the JTAG Configuration Manager (JCM) previously created at BYU. The JCM consists of a custom I/O board paired with a MicroZed development board which includes a Xilinx ZYNQ SoC. This platform is used to implement a flexible configuration management system that can communicate with Xilinx FPGAs at high speeds using the JTAG and SelectMAP interfaces.The improved system described in this thesis increases the maximum data transfer rate of the JCM's JTAG and SelectMAP interfaces and dramatically decreases the processor utilization of user programs running on the JCM. This is accomplished by incorporating a Direct Memory Access (DMA) engine and interrupts into the system. In addition to faster data rates, these changes and the decrease in processor utilization also allow the JCM to manage up to eight JTAG chains simultaneously with the use of a special I/O card.

The project deals with the testing of SRAM memories using method MBIST with the utilisation of sofware tool Tessent Memory BIST. The main purpose is to get familiar with memory testing and to create a design for testing on a specific chip which after its implementation on the chip will retain the original features and functions. Subsequently, the tool is evaluated on its usability.

In this thesis I aim at a design of the laboratory kit and study ways how to programme CPLD devices made by Altera company. The product is used for development and demonstration of applications in CPLD devices made by Altera company. The kit is designed for Altera programming cables and Presto (made by ASIX). Input signals are implemented by a set of switches and buttons on the board. Output states are displayed by LED diods, possibly connected to multiplex the display. The user can connect to external devices via external inputs. Thesis is also aimed at the design PCB of the laboratory kit, subsequent production, recovery and verification of compatibility ALTERA and PRESTO programmers. End of the thesis aims on working with the Quartus II design environment. In particular, it is a guide to working with templates and simulation of VHDL designs.