Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 77-81). Also available on the World Wide Web.

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

This thesis presents a low power DC-DC converter suitable for harvesting energy from high impedance thermoelectric generators (TEGs) for the use in body powered electronics. The chip has been fabricated in a 130nm CMOS technology. To meet the power demands of body powered networks, a novel dual-path architecture capable of efficiently harvesting power at levels below 5 μW has been developed. To control the converter, a low power control loop has been developed. The control loop features a low-power clock and a pulse counting system that is capable of matching the converter impedance with high impedance TEGs. The system consumes less than 900nW of quiescent power and maintains an efficiency of 68% for a load of 5 μW. / Graduation date: 2013

New low power solutions for Very Large Scale Integration (VLSI) are proposed. Especially, we focus on leakage power reduction. Although neglected at 0.18u technology and above, leakage power is nearly equal to dynamic power consumption in nanoscale technology, e.g., 0.07u. We present a novel circuit structure, we call it sleepy stack, which is a combination of two well-known low-leakage techniques: the forced stack and sleep transistor techniques. Unlike the forced stack technique, the sleepy stack technique can utilize high-Vth transistors without incurring a large delay increase. Also, unlike the sleep transistor technique, the sleepy stack technique can retain exact logic state while achieving similar leakage power savings. In short, our sleepy stack structure achieves ultra-low leakage power consumption while retaining logic state. We apply the sleepy stack technique to both generic logic circuits as well as SRAM. At 0.07u technology, the sleepy stack logic circuits achieves up to 200X leakage reduction compared the forced stack technique with small (under 7%) delay variations and 51~118% area overheads. The sleepy stack SRAM cell with 1.5xVth achieves 5X leakage reduction with 32% delay increase or 2.49X leakage reduction without delay increase compared to the high-Vth SRAM cell. As such, the sleepy stack technique can be applicable to a design that requires ultra-low leakage power with quick response time while paying area and delay cost. We also propose a new low power architectural technique named Low-Power Pipelined Cache (LPPC). Although a conventional pipelined cache is mainly used to reduce cache access time, we lower supply voltage of cache using LPPC to save dynamic power. We achieve 20.43% processor dynamic energy savings with 4.14% execution cycle increase using 2-stage low-Vdd LPPC. Furthermore, we apply LPPC to the sleepy stack SRAM. The sleepy stack pipelined SRAM achieves 17X leakage power reduction while increasing execution time by 4% on average. Although this combined technique increases active power consumption by 33%, this technique is well suited for the system that spends most of its time in sleep mode.

Since large scale unscheduled tripping of wind power generation could lead to power system stability problem. Thus network interconnection regulations become more rigid when the wind power penetration reaches a non-neglible portion of the total power generation. This thesis presents a comparison of five different low voltage ride through (LVRT) capability enhancement technologies, i.e., additional rotor resistance, DC bus chopper, crowbar on rotor, the combination of above schemes, and grid voltage support by controlling grid side converter. System simulations are performed under Digsilent environment with model and control blocks provided by the package. Additional models are developed to implement the LVRT enhancement schemes studied. A Doubly-Fed Induction Generator (DFIG) with pitch control is used to simulate different system fault scenarios with different voltage sag magnitude and duration time. Simulation results indicate that different enhancement schemes provide various levels in relieving DC bus overvoltage, rotor winding overcurrent, and overspeed problems, and the method combines all tested schemes seems to provide the best result.

Distributed generation (DG) has received much attention recently due to environmental consciousness and rising of the energy efficiency. However, DG interconnecting to low-voltage distribution system may cause voltage variation, and a lot of single-phase DG or single-phase load may result in voltage unbalance. This thesis presents a distributed-STATCOM (D-STATCOM) to alleviate variation of both positive-sequence and negative-sequence voltages at the fundamental frequency. The D-STATCOM operates as susceptance and conductance at the fundamental positive-and negative-sequence frequency, respectively. The susceptance and conductance commands are dynamically tuned according to voltage fluctuation at the installation location. Therefore, the positive-sequence voltage can be restored to the nominal value as well as the negative-sequence voltage can be suppressed to an allowable level. Computer simulations and experimental results verify the effectiveness of the proposed control strategy.

Demand is emerging for offshore wind power plant (WPP) that often has favorable capacity factor and high capacity value as compared with onshore wind farms. There are many challenges regarding power losses, economics, protection system and reliability of the wind farm. Collection system design decisions play an essential role to efficient operation of the WPP. Wind generators also have to be able to cope with grid disturbances. Low voltage ride-through (LVRT) capability of wind turbines requires generator units remain in operation for severe voltage drops during ¡@grid system faults, and be able to withstand depressed voltage for a few seconds in a recovery period. Technical requirements set out in grid codes for off shore wind farm normally relate to different connection points. A rigor LVRT requirement would increase the overall investment costs of the wind farm. In most offshore wind farm projects, radial collector systems connecting a number of wind turbines and terminated at the offshore platform have served well the requirements for an economical design. However, due to the lack of redundancy, its reliability is poor. To improve the reliability of the collector system, the inclusion of a cable section that interconnects the remote ends of two adjacent radial feeders has been proposed. The transmission system of a wind farm takes the power generated and sends it to shore. Medium voltage AC transmission is the simplest one, just gathering the cables from the collector system and taking them together until they reach the point of common coupling (PCC).Through wind farm dynamic simulations by using DIgSIENT package, this thesis demonstrates that the ride through capability which occur at the particular wind parks with different collector system topology are greater than those which the wind turbines are capable of riding through, i.e., LVRT curves of different wind farm collection system designs of an offshore WPP and a single wind generator are different. This can be exploited to reduce the cost in complying with LVRT requirement of offshore WPP.

This paper is the use of the active inductor instead of passive inductors to save area, enter the match aspects of the use of the feedback capacitor in parallel with the resistor to achieve matching with the control input voltage, in addition to adjusting the feedback resistor can control the noise. The LNA dissipates 13.2 mW power and achieves input return loss (S11) below -10dB, output return loss (S22) below -10 dB, forward gain (S21) of 11.3~14.5dB, reverse isolation (S12) below -40dB, and noise figure (NF) of 3~3.18 dB. 1-dB compression point (P1dB) of -24 dBm and input third-order inter-modulation point (IIP3) of -14 dBm .

A low voltage low power sigma¡Vdelta modulator for voice applications is presented. The implementation of proposed sigma-delta modulator is based on switched-capacitor circuit. Bootstrapped switches were used to replace CMOS transmission gates for increasing the insufficient driving of switched-capacitor circuit under the low voltage operation. To reduce the power dissipation, an improved current mirror OTA were designed with rail-to-rail output swing, which can also make the voltage gain enhance 10~20 dB and overcome the poor voltage gain shortage of traditional current mirror OTA. The post-simulation result shows that the modulator achieves a dynamic range of 77 dB, a peak signal-to-noise ratio of 82 dB, and the sigma-delta modulator dissipates 25£gW under 1.1-V voltage supply, using TSMC 0.18£gm 1P6M CMOS technology.

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.