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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
221

The role of North Atlantic Current water in exchanges across the Greenland-Scotland Ridge from the Nordic Seas

More, Colin 06 1900 (has links)
The circulation and gradual transformation in properties of oceanic water masses is a matter of great interest for short-term weather and biological forecasting, as well as long-term climate change. It is usually agreed that the Nordic Seas between Greenland and Norway are key to these transformations since they are an important producer of dense water, a process central to the theory of the global thermohaline circulation. In this study, one component of this deep water is examined – that formed in the Nordic Seas themselves from the inflowing North Atlantic Current. Using Lagrangian particle tracking applied to a 50-year global ocean hindcast simulation, it is concluded that only about 6% of the inflowing North Atlantic Current is thus transformed, and that most of these transformations occur in boundary currents. Furthermore, it is found that the densified North Atlantic water attains only medium depths instead of joining the deep overflows. The model’s poor representation of vertical mixing, however, limits the applicability of this study to deep water formation.
222

Sun-perturbed dynamics of a particle in the vicinity of the Earth-Moon triangular libration points

Munoz, Jean-Philippe, January 1900 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.
223

On Lagrangian meshless methods in free-surface flows

Silverberg, Jon P. January 2005 (has links) (PDF)
Thesis (Master of Engineering in Ocean Engineering)--University of California at Berkeley, 2004. / "January 2005." Description based on title screen as viewed on May 25, 2010. DTIC Descriptor(s): Fluid Dynamics, Lagrangian Functions, Equations Of Motion, Acceleration, Formulations, Grids, Continuum Mechanics, Gaussian Quadrature, Derivatives (Mathematics), Compact Disks, Boundary Value Problems, Polynomials, Interpolation, Pressure, Operators (Mathematics). DTIC Identifier(s): Multimedia (CD-Rom), Moving Grids, Meshless Discretization, Lifs (Lagrange Implicit Fraction Step), Lagrangian Dynamics, Meshless Operators, Mlip (Multidimensional Lagrange Interpolating Polynomials), Flux Boundary Conditions, Radial Basis Functions Includes bibliographical references (58-59).
224

Limitantes inferiores par ao problema de dimensionamento de lotes em máquinas paralelas /

Fiorotto, Diego Jacinto. January 2011 (has links)
Orientador: Silvio Alexandrede Araujo / Banca: Bernardo Sobrinho Simões de Almada Lobo / Banca: Franklina Maria Bragion Toledo / Resumo: O problema de dimensionamento de lotes é um problema de otimização da produção, em que o objetivo é planejar a quantidade de itens a ser produzida em várias, ou única, máquinas em cada período ao longo do horizonte de tempo, de modo a tender uma demanda e otimizar uma função objetivo. Este trabalho aborda o problema de dimensionamento de lotes em um único estágio em um ambiente com máquinas paralelas distintas. Cada item pode ser produzido em qualquer máquina, acarretando um tempo de preparação que é gasto antes de começar a produção. O objetivo do trabalho consiste em obter limitantes inferiores de boa qualidade para este problema. Para tanto, é desenvolvido um método de solução baseado numa reformulação do problema a e na relaxação lagrangiana de um conjunto de restrições. Alguns resultados computacionais são apresentados algumas propostas futuras para a continuidade do trabalho. / Abstract: The lot-sizing problem is a production optimization problem, where the objective is to plan the quantity of items to be produced in multiple, or single, machines in each period over a time horizon, in order to satisfy a demand and optimize an objective function. This work addresses the single stage parallel machine lot-sizing problem. Each item can be produced on any machine, and incur a setup time before to start the production. The objective of this work is to lower bounds of good quality for this problem. A solution method is developed based on a reformulation of the problem and the Lagrangian relaxation of a set of constrainsts. Some computational results are presented comparing the proposed method with a method from the literature, and, some future researches are proposed. / Mestre
225

Using the eddy covariance technique to measure gas exchanges in a beef cattle feedlot

Prajapati, Prajaya January 1900 (has links)
Doctor of Philosophy / Department of Agronomy / Eduardo Alvarez Santos / Measurements of methane (CH₄) emissions from livestock production could provide invaluable data to reduce uncertainties in the global CH₄ budget and to evaluate mitigation strategies to lower greenhouse gas (GHG) emissions. The eddy covariance (EC) technique has recently been applied as an alternative to measure CH₄ emissions from livestock systems, but heterogeneities in the source area and fetch limitations impose challenges to EC measurements. The main objectives of this study were to: 1) assess the performance of a closed-path EC system for measuring CH₄, CO₂, and H₂0 fluxes; 2) investigate the spatial variability of the EC fluxes in a cattle feedlot using flux footprint analysis; 3) estimate CH₄ emission rates per animal (Fanimal) from a beef cattle feedlot using the EC technique combined with two footprint models: an analytical footprint model (KM01) and a parametrization of a Lagrangian dispersion model (FFP); and 4) compare CH₄ emissions obtained using the EC technique and a footprint analysis with CH₄ emission estimates provided by a well-stablished backward-Lagrangian stochastic (bLS) model. A closed-path EC system was used to measure CH₄, CO₂, and H₂0 fluxes. To evaluate the performance of this closed-path system, a well-stablished open-path EC system was also deployed on the flux tower to measure CO₂ and H₂0 exchange. Methane concentration measurements and wind data provided by that system were used to estimate CH₄ emissions using the bLS model. The performance assessment that included comparison of gas cospectra and measured fluxes from the two EC systems showed that the closed-path system was suitable for the EC measurements. Flux values were quite variable during the field experiment. A one-dimensional flux footprint model was useful to interpret some of the flux temporal and spatial dynamics. Then, a more comprehensive data analysis was carried out using two-dimensional footprint models (FFP and KM01) to interpret fluxes and scale fluxes measured at landscape to animal level. The monthly average Fanimal, calculated using the footprint weighed stocking density ranged from 83 to 125 g animal⁻¹ d⁻¹ (KM01) and 75–114 g animal⁻¹ d⁻¹ (FFP). These emission values are consistent with the results from previous studies in feedlots however our results also suggested that in some occasions the movement of animals on the pens could have affected CH₄ emission estimates. The results from the comparisons between EC and bLS CH₄ emission estimates show good agreement (0.84; concordance coefficient) between the two methods. In addition, the precision of the EC as compared to the bLS estimates was improved by using a more rigorous fetch screening criterion. Overall, these results indicate that the eddy covariance technique can be successfully used to accurately measure CH₄ emissions from feedlot cattle. However, further work is still needed to quantify the uncertainties in Fanimal caused by errors in flux footprint model estimates and animal movement.
226

Discrete gate sizing and timing-driven detailed placement for the design of digital circuits / Dimensionamento de portas discreto e posicionamento detalhado dirigido a desempenho para o projeto de circuitos digitais

Flach, Guilherme Augusto January 2015 (has links)
Ferramentas de projeto de circuitos integrados (do inglˆes, electronic design automation, ou simplesmente EDA) tˆem um papel fundamental na crescente complexidade dos projetos de circuitos digitais. Elas permitem aos projetistas criar circuitos com um n´umero de componentes ordens de grandezas maior do que seria poss´ıvel se os circuitos fossem projetados `a m˜ao como nos dias iniciais da microeletrˆonica. Neste trabalho, dois importantes problemas em EDA ser˜ao abordados: dimensionamento de portas e posicionamento detalhado dirigido a desempenho. Para dimensionamento de portas, uma nova metodologia de relaxac¸ ˜ao Lagrangiana ´e apresentada baseada em informac¸ ˜ao de temporarizac¸ ˜ao locais e propagac¸ ˜ao de sensitividades. Para posicionamento detalhado dirigido a desempenho, um conjunto de movimentos de c´elulas ´e criado usando uma formac¸ ˜ao ´otima atenta `a forc¸a de alimentac¸ ˜ao para o balanceamento de cargas. Nossos resultados experimentais mostram que tais t´ecnicas s˜ao capazes de melhorar o atual estado-da-arte. / Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it would be possible by designing circuits by hand as was done in the early days of microelectronics. In this work, two important EDA problems are addressed: gate sizing and timing-driven detailed placement. They are studied and new techniques developed. For gate sizing, a new Lagrangian-relaxation methodology is presented based on local timing information and sensitivity propagation. For timing-driven detailed placement, a set of cell movement methods are created using drive strength-aware optimal formulation to driver/sink load balancing. Our experimental results shows that those techniques are able to improve the current state-of-the-art.
227

Cell selection to minimize power in high-performance industrial microprocessor designs / Seleção de portas lógicas para minimização de potência em projetos de microprocessadores de alto desempenho

Reimann, Tiago Jose January 2016 (has links)
Este trabalho aborda o problema de dimensionamento portas lógicas e assinalamento de Vt para otimização de potência, área e temporização em circuitos integrados modernos. O fluxo proposto é aplicado aos conjuntos de circuitos de teste dos Concursos do International Symposium on Physical Design (ISPD) de 2012 e 2013. Este fluxo também é adapatado e avaliado nos estágios pós posicionamento e roteamento global em projetos industriais de circuitos integrados, que utilizam uma ferramenta precisa de análise estática de temporização. As técnicas propostas geram as melhores soluções para todos os circuitos de teste do Concurso do ISPD 2013 (no qual foi a ferramenta vencedora), com em média 8% menos consumo de potência estática quando comparada com os outros concorrentes. Além disso, após algumas modificações nos algoritmos, nós reduzimos o consumo em mais 10% em média a pontência estáticas com relação aos resultados do concurso. O foco deste trabalho é desenvolver e aplicar um algoritmo estado-da-arte de seleção portas lógicas para melhorar ainda mais projetos industriais de alto desempenho já otimizados após as fases de posicionamento e roteamento do fluxo de projeto físico industrial. Vamos apresentar e discutir vários problemas encontrados quando da aplicação de técnicas de otimização global em projetos industriais reais que não são totalmente cobertos em publicações encontradas na literatura. Os métodos propostos geram as melhores soluções para todos os circuitos de referência no Concurso do ISPD 2013, no qual foi a solução vencedora. Considerando a aplicação industrial, as técnicas propostas reduzem a potência estática em até 18,2 %, com redução média de 10,4 %, sem qualquer degradação na qualidade de temporização do circuito. / This work addresses the gate sizing and Vt assignment problem for power, area and timing optimization in modern integrated circuits (IC). The proposed flow is applied to the Benchmark Suites of the International Symposium on Physical Design (ISPD) 2012 and 2013 Contests. It is also adapted and evaluated in the post placement and post global routing stage of an industrial IC design flow using a sign-off static timing analysis engine. The proposed techniques are able to generate the best solutions for all benchmarks in the ISPD 2013 Contest (in which we were the winning team), with on average 8% lower leakage with respect to all other contestants. Also, after some refinements in the algorithms, we reduce leakage by another 10% on average over the contest results. The focus of this work is to develop and apply a state-of-the-art cell selection algorithm to further improve already optimized high-performance industrial designs after the placement and routing stages of the industrial physical design flow. We present the basic concepts involved in the gate sizing problem and how earlier literature addresses it. Several problems found when applying global optimization techniques in real-life industrial designs, which are not fully covered in publications found in literature, are presented and discussed. Considering the industrial application, the proposed techniques reduce leakage power by up to 18.2%, with average reduction of 10.4% without any degradation in timing quality.
228

The Domain Dependence of Chemotaxis in a Two-Dimensional Turbulent Flow

January 2015 (has links)
abstract: Presented is a study on the chemotaxis reaction process and its relation with flow topology. The effect of coherent structures in turbulent flows is characterized by studying nutrient uptake and the advantage that is received from motile bacteria over other non-motile bacteria. Variability is found to be dependent on the initial location of scalar impurity and can be tied to Lagrangian coherent structures through recent advances in the identification of finite-time transport barriers. Advantage is relatively small for initial nutrient found within high stretching regions of the flow, and nutrient within elliptic structures provide the greatest advantage for motile species. How the flow field and the relevant flow topology lead to such a relation is analyzed. / Dissertation/Thesis / Masters Thesis Mathematics 2015
229

Cell selection to minimize power in high-performance industrial microprocessor designs / Seleção de portas lógicas para minimização de potência em projetos de microprocessadores de alto desempenho

Reimann, Tiago Jose January 2016 (has links)
Este trabalho aborda o problema de dimensionamento portas lógicas e assinalamento de Vt para otimização de potência, área e temporização em circuitos integrados modernos. O fluxo proposto é aplicado aos conjuntos de circuitos de teste dos Concursos do International Symposium on Physical Design (ISPD) de 2012 e 2013. Este fluxo também é adapatado e avaliado nos estágios pós posicionamento e roteamento global em projetos industriais de circuitos integrados, que utilizam uma ferramenta precisa de análise estática de temporização. As técnicas propostas geram as melhores soluções para todos os circuitos de teste do Concurso do ISPD 2013 (no qual foi a ferramenta vencedora), com em média 8% menos consumo de potência estática quando comparada com os outros concorrentes. Além disso, após algumas modificações nos algoritmos, nós reduzimos o consumo em mais 10% em média a pontência estáticas com relação aos resultados do concurso. O foco deste trabalho é desenvolver e aplicar um algoritmo estado-da-arte de seleção portas lógicas para melhorar ainda mais projetos industriais de alto desempenho já otimizados após as fases de posicionamento e roteamento do fluxo de projeto físico industrial. Vamos apresentar e discutir vários problemas encontrados quando da aplicação de técnicas de otimização global em projetos industriais reais que não são totalmente cobertos em publicações encontradas na literatura. Os métodos propostos geram as melhores soluções para todos os circuitos de referência no Concurso do ISPD 2013, no qual foi a solução vencedora. Considerando a aplicação industrial, as técnicas propostas reduzem a potência estática em até 18,2 %, com redução média de 10,4 %, sem qualquer degradação na qualidade de temporização do circuito. / This work addresses the gate sizing and Vt assignment problem for power, area and timing optimization in modern integrated circuits (IC). The proposed flow is applied to the Benchmark Suites of the International Symposium on Physical Design (ISPD) 2012 and 2013 Contests. It is also adapted and evaluated in the post placement and post global routing stage of an industrial IC design flow using a sign-off static timing analysis engine. The proposed techniques are able to generate the best solutions for all benchmarks in the ISPD 2013 Contest (in which we were the winning team), with on average 8% lower leakage with respect to all other contestants. Also, after some refinements in the algorithms, we reduce leakage by another 10% on average over the contest results. The focus of this work is to develop and apply a state-of-the-art cell selection algorithm to further improve already optimized high-performance industrial designs after the placement and routing stages of the industrial physical design flow. We present the basic concepts involved in the gate sizing problem and how earlier literature addresses it. Several problems found when applying global optimization techniques in real-life industrial designs, which are not fully covered in publications found in literature, are presented and discussed. Considering the industrial application, the proposed techniques reduce leakage power by up to 18.2%, with average reduction of 10.4% without any degradation in timing quality.
230

Discrete gate sizing and timing-driven detailed placement for the design of digital circuits / Dimensionamento de portas discreto e posicionamento detalhado dirigido a desempenho para o projeto de circuitos digitais

Flach, Guilherme Augusto January 2015 (has links)
Ferramentas de projeto de circuitos integrados (do inglˆes, electronic design automation, ou simplesmente EDA) tˆem um papel fundamental na crescente complexidade dos projetos de circuitos digitais. Elas permitem aos projetistas criar circuitos com um n´umero de componentes ordens de grandezas maior do que seria poss´ıvel se os circuitos fossem projetados `a m˜ao como nos dias iniciais da microeletrˆonica. Neste trabalho, dois importantes problemas em EDA ser˜ao abordados: dimensionamento de portas e posicionamento detalhado dirigido a desempenho. Para dimensionamento de portas, uma nova metodologia de relaxac¸ ˜ao Lagrangiana ´e apresentada baseada em informac¸ ˜ao de temporarizac¸ ˜ao locais e propagac¸ ˜ao de sensitividades. Para posicionamento detalhado dirigido a desempenho, um conjunto de movimentos de c´elulas ´e criado usando uma formac¸ ˜ao ´otima atenta `a forc¸a de alimentac¸ ˜ao para o balanceamento de cargas. Nossos resultados experimentais mostram que tais t´ecnicas s˜ao capazes de melhorar o atual estado-da-arte. / Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it would be possible by designing circuits by hand as was done in the early days of microelectronics. In this work, two important EDA problems are addressed: gate sizing and timing-driven detailed placement. They are studied and new techniques developed. For gate sizing, a new Lagrangian-relaxation methodology is presented based on local timing information and sensitivity propagation. For timing-driven detailed placement, a set of cell movement methods are created using drive strength-aware optimal formulation to driver/sink load balancing. Our experimental results shows that those techniques are able to improve the current state-of-the-art.

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