Double cantilever beam (DCB) specimens with distinct intermetallic microstructures and different geometries were fractured under different mode ratios of loading, ψ, to obtain critical strain energy release rate, Jc. The strain energy release rate at crack initiation, Jci, increased with phase angle, ψ, but remained unaffected by the joint geometry. However, the steady-state energy release rate, Jcs, increased with the solder layer thickness. Also, both the Jci and Jcs decreased with the thickness of the intermetallic compound layer. Next, mode I and mixed-mode fracture tests were performed on discrete (l=2 mm and l=5 mm) solder joints arranged in a linear array between two copper bars to evaluate the J = Jci (ψ) failure criteria using finite element analysis. Failure loads of both the discrete joints and the joints in commercial electronic assemblies were predicted reasonably well using the Jci from the continuous DCBs. In addition, the mode-I fracture of the discrete joints was simulated with a cohesive zone model which predicted reasonably well not only the fracture loads but also the overall load-displacement behavior of the specimen. Additionally, the Jci calculated from FEA were verified estimated from measured crack opening displacements in both the continuous and discrete joints. Finally, the pad-crater fracture mode of solder joints was characterized in terms of the Jci measured at various mode ratios, ψ. Specimens were prepared from lead-free chip scale package-PCB assemblies and fractured at low and high loading rates in various bending configurations to generate a range of mode ratios. The specimens tested at low loading rates all failed by pad cratering, while the ones tested at higher loading rates fractured in the brittle intermetallic layer of the solder. The Jci of pad cratering increased with the phase angle, ψ, but was independent of surface finish and reflow profile. The generality of the J =Jci(ψ) failure criterion to predict pad cratering fracture was then demonstrated by predicting the fracture loads of single lap-shear specimens made from the same assemblies.

Double cantilever beam (DCB) specimens with distinct intermetallic microstructures and different geometries were fractured under different mode ratios of loading, ψ, to obtain critical strain energy release rate, Jc. The strain energy release rate at crack initiation, Jci, increased with phase angle, ψ, but remained unaffected by the joint geometry. However, the steady-state energy release rate, Jcs, increased with the solder layer thickness. Also, both the Jci and Jcs decreased with the thickness of the intermetallic compound layer. Next, mode I and mixed-mode fracture tests were performed on discrete (l=2 mm and l=5 mm) solder joints arranged in a linear array between two copper bars to evaluate the J = Jci (ψ) failure criteria using finite element analysis. Failure loads of both the discrete joints and the joints in commercial electronic assemblies were predicted reasonably well using the Jci from the continuous DCBs. In addition, the mode-I fracture of the discrete joints was simulated with a cohesive zone model which predicted reasonably well not only the fracture loads but also the overall load-displacement behavior of the specimen. Additionally, the Jci calculated from FEA were verified estimated from measured crack opening displacements in both the continuous and discrete joints. Finally, the pad-crater fracture mode of solder joints was characterized in terms of the Jci measured at various mode ratios, ψ. Specimens were prepared from lead-free chip scale package-PCB assemblies and fractured at low and high loading rates in various bending configurations to generate a range of mode ratios. The specimens tested at low loading rates all failed by pad cratering, while the ones tested at higher loading rates fractured in the brittle intermetallic layer of the solder. The Jci of pad cratering increased with the phase angle, ψ, but was independent of surface finish and reflow profile. The generality of the J =Jci(ψ) failure criterion to predict pad cratering fracture was then demonstrated by predicting the fracture loads of single lap-shear specimens made from the same assemblies.

Sn-Pb solder has long been used in the Electronics industry. But, due to its toxic nature and environmental effects, certain restrictions are made on its use and therefore many researchers are looking to replace it. Sn-3.0Ag-0.5Cu (SAC) solders are suggested as lead-free replacements but their coarse microstructure and formation of hard and brittle Inter-Metallic Compounds (IMCs) like Ag₃Sn and Cu₆Sn₅ have limited their use in high temperature applications. In this research work, RE elements, mostly lanthanum (La), are used as potential additives to SAC alloys. They reduce the surface free energy, refine the grain size and improve the mechanical and wetting properties of SAC alloys. An extensive experimental work has been performed on the microstructure evolution, bulk mechanical properties, individual phase (matrix and IMCs) mechanical properties, creep behavior and wettability performance of the SAC and SAC-La alloys, with different (La) doping. SEM and EDS have been used to follow the continuous growth of the IMCs at 150°C and 200°C and thus provide a quantitative measure in terms of their size, spacing and volume fraction. Grain size is measured at regular intervals starting from 10 hours up to 200 hours of thermal aging using Optical Microscope with cross polarized light. Bulk mechanical properties are evaluated using tensile tests at low strain rates. Individual phase mechanical properties like Young's modulus, hardness, strain rate sensitivity index and bulge effects are characterized with nanoindentation from 100 µN up to 5000 µN loadings at different temperatures of 25°C, 45°C, 65°C and 85°C. Creep experiments are performed at elevated temperatures with good fitting of Dorn creep and back-stress creep models. Activation energy measurements are made at 40°C, 80°C and 120°C. Wettability testing on copper substrates is used for surface tension, wetting force and contact angle measurements of SAC and SAC-La doped alloys at 250°C and 260°C.

Graduation thesis is specialized on dilemma of the integrated circuits with ball grid array. Chapter two describes several types of packages and confrontation of their characteristics. Chapter three considers possibilities of corrections these boards bedded with packages, mounting and demounting of these packages, method of camera control and also inspection of the soldering process. Chapter four attend to practical measuring of thermal profiles and their optimalization.

This diplomas thesis deals with specific technologies and manufacture of BGA and QFN packages. Also summarizes the most used test methods for assessing the reliability for. Describes the making of equipment for soldering in a nitrogen atmosphere, followed by comparison solder joints of BGA and QFN forming in different atmosphere. Finally, summarizes knowledge about the process of soldering and desoldering lead-free solders for BGA packages, followed by experimental evaluation of the causes of malfunction of repaired samples.

The doctoral thesis is focused on reliability of lead-free solder SAC 305. Knowledge in the field of fatigue models used in determining the lifetime of solder joints are observed in this thesis. Also such methods of predicting reliability as numerically-analytical methods or reliability experimental tests are mentioned. Practical results of reliability measurement are presented. Experimental data served as the foundation for determining empirical coefficients for the fatigue model based on deformation induced by creep of the solder, which was implemented in the ANSYS environment. Results from different methods were compared and conclusions discussing the suitability of the presented prediction methods are formulated.

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100 nm near the transistors and 1000 nm away from the transistors close to the solder bumps. In such BEOL layered stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers. This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode-mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode-mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data. In addition, nanoindenter-based shear test technique designed specifically for this study is demonstrated. The new test technique can address different mode mixities compared to the other interfacial fracture characterization tests, is sensitive to capture the change in fracture parameter due to changes in local trace pattern variations around the vicinity of bump and the test mimics the forces experienced by the bump during flip-chip assembly reflow process. Through this experimental and theoretical modeling research, guidelines are also developed for the reliable design of BEOL stacks for current and next-generation microelectronic devices.