M.Ing. / The aim of this investigation was to determine the N1 value in the relationship between pressure and flow for different types of water reticulation pipes with different forms of fractures. The relationship is defined as: Once these N1 values are established, they can be used as an indication for better pressure management in water reticulation networks. This investigation was limited to three types of pipe with diameter 110 mm and wall thickness of 4 mm: • uPVC • Cast iron • Steel And three different forms of failures: • Round holes • Longitudinal splits • Circular cracks Pressure step testing was used to obtain experimental data. During analysis of the data, Cd was calculated from the initial area of a fracture and kept constant thereafter. Conclusions could be drawn about similar type pipes with similar fractures and comparisons could be made between all the samples as well as previous studies. Generally it seems that longitudinal splits lead to the most excessive leaking, followed by round holes and then the circular cracks. A summary of typical N1 exponents found is shown below: • uPVC pipes with round holes 0.48 - 0.49 • uPVC pipes with longitudinal splits 0.89 - 1.26 • uPVC pipes with circular cracks 0.31 – 0.48 • Cast Iron pipes with round holes 0.43 – 0.44 • Cast Iron pipes with longitudinal splits 0.42 – 0.46 • Cast Iron pipes with circular cracks 0.41 – 0.43 • Steel pipes with round holes 0.42 – 0.44 • Steel pipes with longitudinal splits 0.39 – 0.45 • Steel pipes with circular cracks 0.38 – 0.48

Memory is an important part of any digital processing system. On-chip SRAM can be found in various levels of the memory hierarchy in a processor and occupies a considerable area of the chip. Leakage is one of the challenges which shrinking of technology has introduced and the leakage of SRAM constitutes a substantial part of the total leakage power of the chip due to its large area and the fact that many of the cells are idle without any access. In this thesis, we introduce asymmetric SRAM cells using stacked transistors which reduce the leakage up to 26% while increasing the delay of the cell by only 1.2% while reducing the read noise margin of the cell by only 15.7%. We also investigate an asymmetric cell configuration in which increases the delay by 33% while reduces the leakage up to 30% and reducing the read noise margin by only 1.2% compared to a regular SRAM cell.

Aggressive scaling of CMOS circuits in recent times has lead to dramatic increase in leakage currents. Previously, sub-threshold leakage current was the only leakage current taken into account in power estimation. But now gate leakage and reverse biased junction band-to-band-tunneling leakage currents have also become significant. Together all the three types of leakages namely sub-threshold leakage, gate leakage and reverse bias junction band-to-band tunneling leakage currents contribute to more than 25% of power consumption in the current generation of leading edge designs. Different sources of leakage can affect each other by interacting through resultant intermediate node voltages. This is called loading effect and it leads to further increase in leakage current. On the other hand, sub-threshold leakage current decreases as more number of transistors is stacked in series. This is called stack effect. Previous works have been done that analyze each type of leakage current and its effect in detail but independent of each other. In this work, a pattern dependent steady state leakage estimation technique was developed that incorporates loading effect and accounts for all three major leakage components, namely the gate leakage, band to band tunneling leakage and sub-threshold leakage. It also considers transistor stack effect when estimating sub-threshold leakage. As a result, a coherent leakage current estimator tool was developed. The estimation technique was implemented on 65nm and 45nm CMOS circuits and was shown to attain a speed up of more than 10,000X compared to HSPICE. This work also extends the leakage current estimation technique in Field Programmable Gate Arrays (FPGAs). A different version of the leakage estimator tool was developed and incorporated into the Versatile Place & Route CAD tool to enable leakage estimation of design after placement and routing. Leakage current is highly dependent on the steady state terminal voltage of the transistor, which depends on the logic state of the CMOS circuit as determined by the input pattern. Consequently, there exists a pattern that will produce the highest leakage current. This work considers all leakage sources together and tries to find an input pattern(s) that will maximize the composite leakage current made up of all three components. This work also analyzes leakage power in presence of dynamic power in a unique way. Current method of estimating total power is to sum dynamic power which is ½&#;CLVDD2f and sub-threshold leakage power. The dynamic power in this case is probabilistic and pattern independent. On the other hand sub-threshold leakage is pattern dependent. This makes the current method very inaccurate for calculating total power. In this work, it is shown that leakage current can vary by more than 8% in time in presence of switching current.

Purpose: Determine the timeframe of bacterial penetration that occurs to the apex when obturation material (gutta percha) is exposed to bacteria for a set period of time (45 days) and to determine if bacterial penetration of the obturated root is influenced by the type of irrigant used during the final rinse (17% EDTA vs 2% Chlorhexidine vs full strength 5.25% NaOCl). Methods: Thirty-six extracted teeth, including six controls, were instrumented and irrigated with 5.25% NaOCl followed by a final rinse of either: 17% EDTA, 2% Chlorhexidine, or 5.25% NaOCl, and then obturated. Each root was suspended between two chambers: the coronal chamber inoculated with brain heart infusion broth and 〖10〗^8 colony-forming units of Enterococcus faecalis, the apical chamber with brain heart infusion broth. The latter was checked daily for turbidity, indicating bacterial leakage. Results: After excluding teeth with clear indications of experimental failure, 21 teeth were included in the analysis. Leakage rates were not significantly difference across the three groups (Chlorhexidine: 14%, EDTA: 67%, NaOCl: 50%; p-value=0.1581). Time to leakage was not significantly difference across the three groups (p-value=0.2470). Conclusion: Within the limitations of this study it was shown that leakage occurs between 4-42 days and that there was no significant difference between the different solutions in preventing leakage.

The paper sheds light upon a specific issue: carbon leakage. Leakage can be understood as an unanticipated net carbon loss or gain, attributable to a climate policy, or reduction activities. Benign leakage effects are harmless. Unsettling are the ones that pose a threat to project’s environmental integrity. The Clean Development Mechanism (CDM) is no exception to such risk. In order to investigate leakage and the corresponding leakage calculation methods addressed in the CDM projects, a qualitative content analysis is conducted on 203 methodologies. Methodology documents serve as ideal textual data for examining CDM related leakage because the development of any new project must be based on methodologies. In relation to the research question, the content analysis synthesizes 11 types of leakage sources. Excluding the case where no leakage is considered, 10 type of leakage sources are then broadly classified as Activity Shift, Market Effects and Life Cycle Leakage. Their corresponding leakage calculation methods are described and reviewed in terms of their geographic reach, and leakage characteristics. A percentage pattern is presented in relation to each sector. The findings are that the vast majority of the CDM leakage calculation methods address primary leakage specific to each individual project at a localized scale, among which, methods addressing Life Cycle Leakage are in the predominant majority. Market Effects as secondary sources are acknowledged as a potential threat to the overall benefit, but the CDM methodologies offer no quantitative method.

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The scaling down of transistor sizes has imposed significant challenges in today's technology. Memories such as eDRAM, are experiencing poor retention time because of challenges such as reference voltage variation, high transistor leakage, and low cell capacitance. It can be seen that we must consider not only the first order effects, but also the second order effects to ensure we keep up with current technology trends such as Moore's law. In this thesis we explore various circuit level techniques on level shifters in order to achieve better retention time. With our research, we have addressed important design challenges and propose techniques that can be utilized in current and emerging technologies. Level shifters (LS) are crucial components in low-power design where the die is segregated in multiple voltage domains. LS are used at the voltage domain interfaces to mitigate sneak path current. A less-known but very important application of LS is in high voltage drivers for designs where voltage boosting is needed for performance and functionality. We first study LS in eDRAM where LS is employed in the wordline path. Our investigation reveals that leakage power of LS can pose a serious threat by lowering the wordline voltage and subsequently affecting the speed and retention time of the eDRAM. It can also be noted that the delay of the LS under worse case process corners can cause significant functional discrepancies. We propose low-power pulsed-LS with supply gating to circumvent these issues. Our analysis indicate that pulsed-LS design can improve the worst case speed from 2.7%-43%. We extended this concept to design generic self-collapsible LSs that can be used for other applications such as voltage interfaces. The self-collapsed design in both applications improved the worst case speed from 6%-24% and 89% in some cases.

Cryogenic composites find critical application in the manufacture of fuel tanks for reusable launch vehicles due to significant reduction in overall structural weight of the tank. These fuel tanks contain pressurized cryogen such as hydrogen at cryogenic temperatures. Exposure to varying temperatures and mechanical loads resulting from flight cycle, containment of pressurized cryogen causes thermo-mechanical loading of the composite. The thermo-mechanical loading cycles combined with anisotropy of the composite and mismatch in the thermal and mechanical properties of fibers and matrix lead to transverse matrix cracks (TMC) in each ply. TMC in adjacent plies intersect in localized regions at ply interfaces called crack junctions, which open up due to delamination on application of thermo-mechanical load. TMC and crack junctions usually form a network of leakage paths that assists leakage of cryogen through the composite. In this study, the volumetric flow rate of cryogen leaking through a damaged cross-ply composite with five plies is determined by estimating the effective conductance of the leakage paths. For a given damage state and applied load, crack junction and TMC openings are obtained by finite element analysis. A computational fluid dynamics model is first used to estimate the effective conductance of a leakage path to hydrogen leakage and then a simplified analytical model is used to compute the effective conductance from individual conductances of each crack junction and TMC through a series-parallel combination. A single phase flow model is considered for the numerical analysis of hydrogen flow through TMC and crack junctions. The simulations are carried out using a commercial computational fluid dynamics software, FLUENT. Parametric studies are carried out to investigate the dependence of leak rate of hydrogen on the irregularities of the TMC geometry and TMC, crack junction openings. The simplified model predictions of the effective conductance for the five ply composite show good comparison with numerical simulations.

Side channel attacks, where an attacker learns some physical information about the state of a device, are one of the ways in which cryptographic schemes are broken in practice. "Provably secure" schemes are subject to these attacks since the traditional models of security do not account for them. The theoretical community has recently proposed leakage resilient cryptography in an effort to account for side channel attacks in the security model. This thesis provides an in-depth look into what security guarantees public key leakage resilient schemes provide in practice.